winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatible

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Sonny Jiang 2015-11-12 12:34:37 -05:00 committed by Marek Olšák
parent 676bc25140
commit 338d7bf053
2 changed files with 5 additions and 2 deletions

View file

@ -352,6 +352,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMicroTiled(
ComputeSurfaceAlignmentsMicroTiled(expTileMode,
pIn->bpp,
pIn->flags,
pIn->mipLevel,
numSamples,
&pOut->baseAlign,
&pOut->pitchAlign,
@ -647,6 +648,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled(
AddrTileMode tileMode, ///< [in] tile mode
UINT_32 bpp, ///< [in] bits per pixel
ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
UINT_32 mipLevel, ///< [in] mip level
UINT_32 numSamples, ///< [in] number of samples
UINT_32* pBaseAlign, ///< [out] base address alignment in bytes
UINT_32* pPitchAlign, ///< [out] pitch alignment in pixels
@ -669,7 +671,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceAlignmentsMicroTiled(
// ECR#393489
// Workaround 2 for 1D tiling - There is HW bug for Carrizo
// where it requires the following alignments for 1D tiling.
if (flags.czDispCompatible)
if (flags.czDispCompatible && (mipLevel == 0))
{
*pBaseAlign = PowTwoAlign(*pBaseAlign, 4096); //Base address MOD 4096 = 0
*pPitchAlign = PowTwoAlign(*pPitchAlign, 512 / (BITS_TO_BYTES(bpp))); //(8 lines * pitch * bytes per pixel) MOD 4096 = 0

View file

@ -315,7 +315,8 @@ private:
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
BOOL_32 ComputeSurfaceAlignmentsMicroTiled(
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples,
AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
UINT_32 mipLevel, UINT_32 numSamples,
UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const;
BOOL_32 ComputeSurfaceAlignmentsMacroTiled(