Commit graph

214445 commits

Author SHA1 Message Date
Samuel Pitoiset
373faab109 radv: use GFX11 packed context regs
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This is supposed to be optimal for the CP. Only for dGPUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38187>
2025-11-05 15:15:00 +00:00
Samuel Pitoiset
db3a79a10a radv: add separate functions for emitting framebuffer on GFX11-11.5
To use packed context registers on dGPUs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38187>
2025-11-05 15:15:00 +00:00
Samuel Pitoiset
58a5f5eb6b radv: add GFX11 packed context registers helpers
Tracked registers aren't in common code yet.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38187>
2025-11-05 15:14:58 +00:00
Samuel Pitoiset
3c5ec268ec amd,radeonsi: add GFX11 packed context registers helpers to common code
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38187>
2025-11-05 15:14:58 +00:00
Alessio Belle
a6ca6bcabf pvr: add device info for GE8300 (22.67.54.30)
Requested by the community [1].

[1] https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/13

Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38211>
2025-11-05 14:47:27 +00:00
Alessio Belle
b83bd94d69 pvr: add device info for GE7800 (15.5.1.64)
Requested by the community [1].

[1] https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/13

Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38211>
2025-11-05 14:47:26 +00:00
Saroj Kumar
8005bf631c radeonsi: Move binary upload, dump code to new file
Moved helper functions for binary upload and dump
code from si_shader.c to new file si_shader_binary.c

Signed-off-by: Saroj Kumar <saroj.kumar@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38166>
2025-11-05 14:30:02 +00:00
Juan A. Suarez Romero
973a950932 v3dv/ci: add timeout in expected list
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38259>
2025-11-05 13:49:00 +00:00
Collabora's Gfx CI Team
fcecfe54e8 Uprev Piglit to 5309e3401d6b03e8a0bb7bfdc1e0f5bc1ad754af
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ec76cc7a31...5309e3401d

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38253>
2025-11-05 12:49:28 +00:00
Kenneth Graunke
183d57aa9e ci: Run intel shader-db on Haswell, Broadwell, and Meteorlake
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This would have caught recent regressions.

Haswell covers crocus.
Broadwell covers iris's oldest platform.
Skylake and derivatives are widely deployed.
Meteorlake is reasonably representative of recent Intel hardware.

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38231>
2025-11-05 10:58:00 +00:00
Kenneth Graunke
96b739b449 elk: Disable IO semantic validation when remapping patch offsets
Marek disabled this for brw in 2f6b4803ab
but elk also needs the fix.  Fixes issues in shader-db/open-subdiv/7 on
crocus targeting Haswell.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38231>
2025-11-05 10:58:00 +00:00
Kenneth Graunke
10e2631e79 iris, crocus: Disable new IO slot validation for FB fetch load_output
This is a framebuffer fetch for blend equation advanced lowering.  We're
using a binding table index as the offset, which is not a slot.

Also, validate the shader after setup_binding_table so that we catch
errors here at the right place, rather than deeper in the compiler.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38231>
2025-11-05 10:58:00 +00:00
Georg Lehmann
b2172467d1 aco/gfx10_3: work around NSA hazard
4+ dword NSA can hang if exec becomes non-zero again directly before
the instruction.

Foz-DB Navi21:
Totals from 608 (0.74% of 82161) affected shaders:
Instrs: 945138 -> 946431 (+0.14%)
CodeSize: 5171580 -> 5176864 (+0.10%)
Latency: 13356895 -> 13357113 (+0.00%)
InvThroughput: 3043234 -> 3043236 (+0.00%); split: -0.00%, +0.00%

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9852
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13981
Cc: mesa-stable

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38215>
2025-11-05 10:06:04 +00:00
David Rosca
bcb6e6b6e6 radv/video: Fix AV1 bidir compound encode with order_hint disabled
Cc: mesa-stable
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37911>
2025-11-05 09:44:04 +00:00
David Rosca
96db490318 radv/video: Don't require encode FW version >= interface version
Otherwise this breaks backwards compatibility when bumping interface
version for new features.

Cc: mesa-stable
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37911>
2025-11-05 09:44:04 +00:00
David Rosca
1a8a8db8c5 radeonsi/vcn: Fix AV1 bidir compound encode with order_hint disabled
Cc: mesa-stable
Reviewed-by: Benjamin Cheng <benjamin.cheng@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37911>
2025-11-05 09:44:04 +00:00
Yiwei Zhang
4201613de1 venus: enable sparse resource support on lavapipe
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Now that lavapipe sparse resource support on external memory has been
fixed, expose sparse resource support from venus on lavapipe. Meanwhile,
make remaining failures explicit (failed in lavapipe as well).

This CL also drops an obsolete comment and updates expectations from
full nightly runs.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:40 +00:00
Yiwei Zhang
125b93595e llvmpipe: support sparse resource with LLVMPIPE_MEMORY_FD_TYPE_OPAQUE
Store a dup fd for OPAQUE type as required by sparse binding. Use
os_map_memory_fd_placed to handle binding for opaque fd backed memory,
while the unbind will still correctly share the same code path with
other cases. This adds sparse resource support with OPAQUE type in
addition to DMA_BUF, and venus no longer has to hide sparse resource on
lavapipe.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:40 +00:00
Yiwei Zhang
0d72b86fe9 llvmpipe: refactor llvmpipe_resource_bind_sparse
Improve readability and prepare for opaque fd support.

No behavior change involved.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:40 +00:00
Yiwei Zhang
532eb04006 llvmpipe: split sparse binding part to llvmpipe_resource_bind_sparse
Since it early returns, refactor our with a dedicated helper for
cleaness and to prepare for further refactors.

No behavior change involved.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:40 +00:00
Yiwei Zhang
ab1902e666 llvmpipe: add fd type INVALID and ANONYMOUS
This is mainly to ensure internal anonymous file based memory allocs do
not collide with opaque fd type. Since we are here, add INVALID type and
assign to non-Linux internal alloc.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:40 +00:00
Yiwei Zhang
8f7543e450 util: add os_map_memory_fd_placed for placed mapping support
This completes the opaque fd api coverage, and is needed by lavapipe for
sparse binding support with opaque fd external memory.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:40 +00:00
Yiwei Zhang
743b9a52d9 util: add get_fd_header helper in os_memory_fd
Prepare for placed mapping.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:40 +00:00
Yiwei Zhang
e8f66ef197 llvmpipe: refactor dmabuf and opaque fd handling
This change:
1. add new helpers to handle dmabuf alloc/import/free
2. use FREE to match with alloc macro
3. simplify opaque fd code path

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:39 +00:00
Yiwei Zhang
4d0fbd1c67 llvmpipe: handle os_dupfd_cloexec failure
Make it easy to debug fd leak or hitting open fd limit.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:39 +00:00
Yiwei Zhang
1be7832f3e llvmpipe: handle mmap failure for lp_texture
This makes debugging easier. Also assert that sparse binding is only
used with resource_create_unbacked.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:39 +00:00
Yiwei Zhang
67d54fd5dc llvmpipe: support sparse resource with LLVMPIPE_MEMORY_FD_TYPE_DMABUF
There's already the type, and there's no concurrent usage of fd and
dmabuf fd, so just drop it. This fixes sparse resource to work with
dmabuf external memory for lavapipe. In addition, this makes sparse
resource from venus on lavapipe to work with dmabuf backing.

Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:39 +00:00
Yiwei Zhang
e0acc5c2b4 llvmpipe: misc fixes for sparse binding
This change:
1. Move size validation within sparse binding, but not escape to
   non-sparse code path.
2. Error out if sparse is requested on unsupported platforms.

Fixes: d747c4a874 ("lavapipe: Implement sparse buffers and images")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:39 +00:00
Yiwei Zhang
66414c6b70 llvmpipe: add a missing alloc error handling in fd import
Fixes: d74ea2c117 ("llvmpipe: Implement dmabuf handling")
Suggested-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:39 +00:00
Yiwei Zhang
3e07f57d4a llvmpipe: fix udmabuf mmap error check
Upon failing to mmap, MAP_FAILED (void *)-1 is returned instead of NULL.

Fixes: d74ea2c117 ("llvmpipe: Implement dmabuf handling")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:39 +00:00
Yiwei Zhang
3a655c212b llvmpipe: zero is also a valid fd
Fixes: a062544d3d ("llvmpipe: Use an anonymous file for memory allocations")
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38074>
2025-11-05 08:26:39 +00:00
Samuel Pitoiset
a0d607bfdb radv,aco: wait for all VMEM loads when the prolog loads large 64-bit attributes
Not the most optimal solution but 64-bit vertex attributes are rarely
used. Could still revisit if we find a real use case that matters.

This fixes recent VKCTS coverage:

dEQP-VK.pipeline.fast_linked_library.vertex_input.component_mismatch.r64g64b64.*_to_dvec2
dEQP-VK.pipeline.shader_object_.*.vertex_input.component_mismatch.r64g64b64.*_to_dvec2

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14243
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38237>
2025-11-05 07:26:45 +00:00
Samuel Pitoiset
ba5bf81aa2 aco: fix reserving VGPRs for 64-bit attributes in VS prologs
Otherwise the fetch index would be overwritten if the attribute format
is 64-bit and more than 2 components are loaded.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14242
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38237>
2025-11-05 07:26:45 +00:00
Eric R. Smith
6f24dad00e panfrost: add 422 AFBC formats
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Most of the infrastructure was already in place for 8 bit (we just
had to add the AFBC mode to use). We also needed to add support for
the 10 bit format (X6R10X6G10_X6R10X6B10_UNORM). Note that this
10 bit format is only supported for AFBC, for linear we have to fall
back to the old multi-plane way of handling it.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
2025-11-04 22:28:03 +00:00
Eric R. Smith
417be4f77e dri: check modifier in dri_create_image_from_winsys
When importing an image, check that the specific combination of
format plus modifier is supported, rather than just checking the
format. This will allow drivers to support some YUV formats in
special cases (specific modifiers, like AFBC for panfrost) while
also allowing us to fall back to generic multi-plane formats when
those modifier+format combinations are not supported by
hardware.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
2025-11-04 22:28:03 +00:00
Eric R. Smith
b11f543c4e mesa: Add R16G16_R16B16_UNORM and related formats
Including the 10 bit variant X6R10X6G10_X6R10X6B10_UNORM. Only the
RG_RB variants seem to have fourccs, so those are the only ones being
added for now, although they would, obviously, be easy to add).

These are used for Y210, Y212, and Y216 fourccs. In particular Y210
is interesting for panfrost, as it is the fourcc used to indicate a
10 bit single plane 4:2:2 encoded as AFBC (similar to how YUYV is
the canonical AFBC for 10 bit 4:2:0).

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
2025-11-04 22:28:03 +00:00
Eric R. Smith
55735b6146 pan: Add 16 bit AFBC support (v10+ only)
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
2025-11-04 22:28:03 +00:00
Eric R. Smith
7a1ef0cf85 panfrost: update AFBC code to handle tiling for 64bpp formats
We had assumed AFBC superblocks were always tiled in an 8x8 pattern,
but this is true only for 32bpp and lower formats; for larger formats
the pattern is 4x4. This isn't an issue yet, but will be when we
support R16G16B16A16 in AFBC.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
2025-11-04 22:28:03 +00:00
Eric R. Smith
3303a04d4f panfrost: add explicit get_dmabuf_modifier_planes override
This is required because otherwise dri2_get_modifier_num_planes will be
confused: dri2_get_mapping_by_fourcc gives the emulated 2 plane YUYV,
but panfrost itself supports a hardware single plane YUYV. This is
arguably a problem with dri2, but other drivers have implemented
dri2_get_modifier_num_planes so we may as well. It also gives us a
hook for supporting more exotic planar configurations, should that
be necessary in the future.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
2025-11-04 22:28:03 +00:00
Eric R. Smith
09b5802f9f panvk: sanity check block size for unorm format
panvk_meta_get_unorm_format_for_blk_size() requires a block size of 4
or less, but we didn't actually check for that before calling it. Fix
that, and also rename the function because what we actually care about
isn't whether it is a unorm format, but a blendable format.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35771>
2025-11-04 22:28:03 +00:00
Sagar Ghuge
43d98a3f1a anv: Use correct engine class for companion RCS
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Fixes: 6f138fe723 ("anv: avoid null pointer access in utrace copies on CCS")
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38247>
2025-11-04 21:39:23 +00:00
spencer-lunarg
17d8a5d8ae lavapipe: Remove trailing whitespace
Signed-off-by: spencer-lunarg <spencer@lunarg.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38223>
2025-11-04 21:20:47 +00:00
Felix DeGrood
faddb5d497 anv/pps: remove assert for double init
pps initializes perf counter multiple times, once from
GpuDataSource::register_data_source and once from
GpuDataSource::OnSetup. This is fine, except we should replace
failing assert with skip on second call.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38224>
2025-11-04 20:54:34 +00:00
Konstantin Seurer
b962063d72 nir: Remove nir_parallel_copy_instr
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Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36483>
2025-11-04 18:51:51 +00:00
Konstantin Seurer
3f3faa82b8 nir/from_ssa: Stop using nir_parallel_copy_instr
nir_parallel_copy_instr can be emulated using an intrinsic for each
entry and an array of arrays that is used by the pass to remember which
copies belong together.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36483>
2025-11-04 18:51:50 +00:00
Konstantin Seurer
b20fd0ef48 nir: Remove parallel copy handling from rewrite_uses_to_load_reg
Parallel copies are only created by nir_convert_from_ssa which does not
use the helper.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36483>
2025-11-04 18:51:50 +00:00
Ian Romanick
67a6fc0160 nir/opt_if: See through inot
Consider

    if (!x) {
       if (x) {
          ...
       }
    }

The inner use of `x` must be false, but so far only instances of `!x`
would have been replaced with a constant. See through the `inot` to
replace instances of `x` as well.

shader-db:

Lunar Lake
total instructions in shared programs: 17205147 -> 17204908 (<.01%)
instructions in affected programs: 56037 -> 55798 (-0.43%)
helped: 79 / HURT: 79

total cycles in shared programs: 879847886 -> 879992944 (0.02%)
cycles in affected programs: 5244138 -> 5389196 (2.77%)
helped: 141 / HURT: 125

Meteor Lake, DG2, and Tiger Lake had similar results. (Meteor Lake shown)
total instructions in shared programs: 19968312 -> 19968069 (<.01%)
instructions in affected programs: 65698 -> 65455 (-0.37%)
helped: 88 / HURT: 104

total cycles in shared programs: 884331007 -> 884469865 (0.02%)
cycles in affected programs: 4839695 -> 4978553 (2.87%)
helped: 172 / HURT: 136

LOST:   3
GAINED: 0

Ice Lake, Skylake, and Broadwell had similar results. (Ice Lake shown)
total instructions in shared programs: 20809765 -> 20809473 (<.01%)
instructions in affected programs: 65976 -> 65684 (-0.44%)
helped: 89 / HURT: 102

total cycles in shared programs: 872466849 -> 872433762 (<.01%)
cycles in affected programs: 5452888 -> 5419801 (-0.61%)
helped: 157 / HURT: 133

total spills in shared programs: 4014 -> 4010 (-0.10%)
spills in affected programs: 30 -> 26 (-13.33%)
helped: 1 / HURT: 0

total fills in shared programs: 3769 -> 3765 (-0.11%)
fills in affected programs: 50 -> 46 (-8.00%)
helped: 1 / HURT: 0

LOST:   3
GAINED: 1

fossil-db:

All Intel platforms had similar results. (Lunar Lake shown)
Totals:
Instrs: 910122459 -> 910097570 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 40045664 -> 40046176 (+0.00%)
Send messages: 40724361 -> 40724036 (-0.00%)
Loop count: 970500 -> 970054 (-0.05%)
Cycle count: 105785543442 -> 105794147978 (+0.01%); split: -0.02%, +0.02%
Spill count: 3426093 -> 3426032 (-0.00%); split: -0.00%, +0.00%
Fill count: 6525296 -> 6525210 (-0.00%); split: -0.00%, +0.00%
Max live registers: 188561553 -> 188519064 (-0.02%); split: -0.02%, +0.00%
Max dispatch width: 47958304 -> 47958496 (+0.00%); split: +0.00%, -0.00%
Non SSA regs after NIR: 227303232 -> 227296055 (-0.00%); split: -0.00%, +0.00%

Totals from 15417 (0.78% of 1977988) affected shaders:
Instrs: 16984488 -> 16959599 (-0.15%); split: -0.20%, +0.05%
Subgroup size: 512 -> 1024 (+100.00%)
Send messages: 900193 -> 899868 (-0.04%)
Loop count: 23059 -> 22613 (-1.93%)
Cycle count: 1200149390 -> 1208753926 (+0.72%); split: -1.48%, +2.20%
Spill count: 25838 -> 25777 (-0.24%); split: -0.29%, +0.06%
Fill count: 43627 -> 43541 (-0.20%); split: -0.28%, +0.08%
Max live registers: 2550741 -> 2508252 (-1.67%); split: -1.75%, +0.08%
Max dispatch width: 296736 -> 296928 (+0.06%); split: +0.08%, -0.02%
Non SSA regs after NIR: 3264670 -> 3257493 (-0.22%); split: -0.25%, +0.03%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38196>
2025-11-04 18:04:00 +00:00
Faith Ekstrand
27d9e4ec2a nvk: VK_EXT_shader_uniform_buffer_unsized_array
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38230>
2025-11-04 17:25:04 +00:00
Georg Lehmann
83e9ae2d5c radv: do not report wave32 in gl_SubgroupSize for Doom Dark Ages
The shaders in question use:

(memory_load + (gl_SubgroupSize - 1)) & ~(gl_SubgroupSize - 1)

My guess is that this is supposed to be the subgroup size of whatever
produced the value, not the subgroup size in this shader.
And because in the consumer the workgroup size is 32, we use wave32.

Fixes: a2d3cbac2a ("radv: determine subgroup/wave size early")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14187

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38214>
2025-11-04 16:52:13 +00:00
Yiwei Zhang
763d2418b8 panvk: fix sample shading of internal blend shader for MSAA
Align with gallium side. When fixed-function blending is not available,
the internal blend shader is used. This is handled by a single ST_TILE
in the blend shader with the current sample ID, which requires sample
shading enablement.

Cc: mesa-stable
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38129>
2025-11-04 16:31:32 +00:00