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Author SHA1 Message Date
Emma Anholt
81bded100c i915g/ci: Add depth-clear-precision-check xfails like everyone else. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
 2022-05-17 07:07:35 -07:00
Emma Anholt
0220348250 ci/crocus: Merge the piglit runs with the deqp runs. 
Fewer manual buttons to click.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
 2022-05-17 07:05:01 -07:00
Emma Anholt
725f56fdb6 ci/crocus: Manual CI updates after CI was down for a bit. 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16390>
 2022-05-17 07:05:01 -07:00
Marek Olšák
265c9af69e Revert "frontend/dri: allow swapped BGR->RGB channel order for MSAA color buffers" 
This reverts commit cfec9a55ea.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16524>
 2022-05-17 11:47:42 +00:00
Marek Olšák
ad50daa982 radeonsi: fix resource_copy_region with ETC formats (e.g. for Stoney) 
Only Stoney, Vega10, Raven, and Raven2 support ETC.

Fixed tests:
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.r11_eac_rgba16i.texture2d_to_texture2d
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.r11_eac_rgba16ui.texture2d_to_texture2d
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.signed_r11_eac_rgba16i.texture2d_to_texture2d
  dEQP-GLES31.functional.copy_image.mixed.viewclass_64_bits_mixed.signed_r11_eac_rgba16ui.texture2d_to_texture2d

Fixes: cf1e562fdd - radeonsi: remove compressed and subsampled gfx copy from resource_copy_region
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6431

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16491>
 2022-05-17 11:26:25 +00:00
Dave Airlie
0a056f84ed llvmpipe: align scratch size to 64-bit size. 
This fixes a crash with luxmark where it uses a 12-byte scratch space,
but when llvmpipe allocates it for 8 lanes, it isn't properly aligned
for 64-bit.

Karol found this debugging rusticl.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16288>
 2022-05-17 11:00:03 +00:00
Marek Olšák
394e42427f winsys/amdgpu: initialize IB_PREAMBLE in advance 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
1fdc3b0fde radeonsi: move CS preamble emission into the winsys 
The preamble will be skipped by the kernel if there is no context switch.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
32c7805ccc radeonsi: merge all preamble states into one 
Tess registers are appended. GS registers are appended or overwritten
if they are already set. There are separate TMZ and non-TMZ preambles.

The preamble will be passed to the kernel as an IB to execute on a context
switch only.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
f46cd73e29 radeonsi/gfx11: optimize attribute stores 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
9b20120d57 radeonsi/gfx11: fix VM faults due to the attribute ring 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
c74d854348 Revert "radeonsi/gfx11: limit MSAA color buffers to the RGBA channel order" 
This reverts commit 54d85700a1.

It's an LLVM bug. If you disable AMDGPUImageIntrinsicOptimizer in LLVM,
MSAA is fixed. There is no LLVM command line option to disable it from Mesa.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
a529e4f7ad radeonsi/gfx11: fix the value of VGT_GS_OUT_PRIM_TYPE at the beginning of IBs 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
a8d2ef8bd6 radeonsi/gfx11: don't insert shader code for GS_PIPELINE_STATS_EMU 
GS_PIPELINE_STATS_EMU is always false, so the branches were never entered.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
fcaa9f5096 radeonsi/gfx11: fix alpha-to-coverage with stencil or samplemask export 
We can't use UINT16_ABGR for the alpha channel. Always use 32_ABGR.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Marek Olšák
af880e591e radeonsi: remove GFX9_MERGED_NUM_USER_SGPR definition 
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
 2022-05-17 10:27:04 +00:00
Tomeu Vizoso
e5acf8016d lima/ci: Disable lima-mali450-piglit-gpu:arm64 
Due to a kernel regression, these jobs fail most of the time with the
backtrace below.

Disable while we get a fix in our kernel.

2022-05-17 08:00:15.428691: [  374.755841] ------------[ cut here ]------------
2022-05-17 08:00:15.428778: [  374.755883] kernel BUG at kernel/irq_work.c:235!
2022-05-17 08:00:15.429011: [  374.759409] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
2022-05-17 08:00:15.429077: [  374.764842] Modules linked in: ipv6
2022-05-17 08:00:15.429233: [  374.768294] CPU: 3 PID: 18210 Comm: vp-bad-program Not tainted 5.16.12linux-v5.16-for-mesa-ci-991fec6622591.tar.bz2 #1
2022-05-17 08:00:15.429386: [  374.778900] Hardware name: Libre Computer AML-S805X-AC (DT)
2022-05-17 08:00:15.429536: [  374.784421] pstate: 60000005 (nZCv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
2022-05-17 08:00:15.429714: [  374.791320] pc : irq_work_run_list+0x64/0x70
2022-05-17 08:00:15.429780: [  374.795546] lr : irq_work_run+0x38/0x50
2022-05-17 08:00:15.429927: [  374.799342] sp : ffff80000801bf30
2022-05-17 08:00:15.430097: [  374.802618] x29: ffff80000801bf30 x28: ffff000003398e00 x27: ffff00000ed3e400
2022-05-17 08:00:15.430158: [  374.809691] x26: ffff800009678750 x25: ffff0000030d8900 x24: ffff800008846fa0
2022-05-17 08:00:15.430316: [  374.816763] x23: ffff800009909f80 x22: 0000000000000006 x21: ffff00000101e780
2022-05-17 08:00:15.430411: [  374.823836] x20: ffff800009d7c408 x19: ffff8000099089c8 x18: 0000000000000000
2022-05-17 08:00:15.430547: [  374.830908] x17: ffff8000252e9000 x16: ffff80000801c000 x15: 0000000000004000
2022-05-17 08:00:15.430735: [  374.837981] x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000001
2022-05-17 08:00:15.430797: [  374.845054] x11: 0000000000000001 x10: ffff8000252e9000 x9 : ffff00002ebf90e0
2022-05-17 08:00:15.430962: [  374.852126] x8 : fffffc00000eda08 x7 : ffff000003398e00 x6 : 0000000000001000
2022-05-17 08:00:15.431029: [  374.859199] x5 : 0000000000000000 x4 : ffff00002ebfc910 x3 : ffff00000ed3e430
2022-05-17 08:00:15.431194: [  374.866271] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff00002ebf19c8
2022-05-17 08:00:15.431261: [  374.873345] Call trace:
2022-05-17 08:00:15.431409: [  374.875761]  irq_work_run_list+0x64/0x70
2022-05-17 08:00:15.431557: [  374.879641]  ipi_handler+0x98/0x15c
2022-05-17 08:00:15.431726: [  374.883091]  handle_percpu_devid_irq+0x88/0x140
2022-05-17 08:00:15.431795: [  374.887576]  generic_handle_domain_irq+0x40/0x60
2022-05-17 08:00:15.431958: [  374.892147]  gic_handle_irq+0x48/0xd0
2022-05-17 08:00:15.432025: [  374.895769]  call_on_irq_stack+0x2c/0x60
2022-05-17 08:00:15.432211: [  374.899651]  do_interrupt_handler+0x80/0x84
2022-05-17 08:00:15.432364: [  374.903791]  el1_interrupt+0x34/0x84
2022-05-17 08:00:15.432432: [  374.907327]  el1h_64_irq_handler+0x1c/0x30
2022-05-17 08:00:15.432616: [  374.911380]  el1h_64_irq+0x78/0x7c
2022-05-17 08:00:15.432764: [  374.914744]  irq_work_queue+0x70/0x80
2022-05-17 08:00:15.432832: [  374.918367]  drm_sched_entity_fini+0x290/0x320
2022-05-17 08:00:15.433043: [  374.922766]  lima_sched_context_fini+0x18/0x24
2022-05-17 08:00:15.433161: [  374.927164]  lima_ctx_free+0x7c/0x114
2022-05-17 08:00:15.433228: [  374.930787]  lima_ioctl_ctx_free+0x28/0x40
2022-05-17 08:00:15.433362: [  374.934840]  drm_ioctl_kernel+0xc4/0x170
2022-05-17 08:00:15.433522: [  374.938721]  drm_ioctl+0x21c/0x440
2022-05-17 08:00:15.433587: [  374.942085]  __arm64_sys_ioctl+0xac/0xf0
2022-05-17 08:00:15.433748: [  374.945966]  invoke_syscall+0x48/0x114
2022-05-17 08:00:15.433814: [  374.949675]  el0_svc_common.constprop.0+0x44/0xec
2022-05-17 08:00:15.433977: [  374.954332]  do_el0_svc+0x28/0x90
2022-05-17 08:00:15.434041: [  374.957609]  el0_svc+0x20/0x60
2022-05-17 08:00:15.434204: [  374.960629]  el0t_64_sync_handler+0x1a8/0x1b0
2022-05-17 08:00:15.434269: [  374.964941]  el0t_64_sync+0x1a0/0x1a4
2022-05-17 08:00:15.434492: [  374.968568] Code: a8c27bfd d50323bf d65f03c0 d65f03c0 (d4210000)
2022-05-17 08:00:15.434612: [  374.974607] ---[ end trace 74ef9d6ff9457a3f ]---
2022-05-17 08:00:15.434676: [  374.979174] Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt
2022-05-17 08:00:15.434888: [  374.986505] SMP: stopping secondary CPUs
2022-05-17 08:00:15.435011: [  374.990391] Kernel Offset: 0x80000 from 0xffff800008000000
2022-05-17 08:00:15.435079: [  374.995818] PHYS_OFFSET: 0x0
2022-05-17 08:00:15.435243: [  374.998665] CPU features: 0x00,00004802,00000846
2022-05-17 08:00:15.435313: [  375.003236] Memory Limit: none
2022-05-17 08:00:15.435488: [  375.006258] ---[ end Kernel panic - not syncing: Oops - BUG: Fatal exception in interrupt ]---

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16554>
 2022-05-17 09:16:21 +00:00
Dave Airlie
8198900071 ac/radv: drop info pointer from the ac and radv shader structs 
This was being used for one bool, just pass the bool.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16521>
 2022-05-17 06:15:25 +00:00
Mike Blumenkrantz
55845409f2 zink: add tu baseline for a630 
oof

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16549>
 2022-05-17 06:04:31 +00:00
Mike Blumenkrantz
fffafa3635 zink: move get_timestamp to screen 
this doesn't need to use a particular context

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16529>
 2022-05-17 03:46:56 +00:00
Mike Blumenkrantz
0befc259a6 zink: use copy context to eliminate dependency on EXT_calibrated_timestamps 
this is unsupported by a surprising number of drivers

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16529>
 2022-05-17 03:46:56 +00:00
Mike Blumenkrantz
9d30d82a9a zink: fix init with MESA_SHADER_CACHE_DISABLE enabled 
Fixes: ba2f5cb20a ("zink: check for error when initializing util_queue")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16533>
 2022-05-17 03:31:10 +00:00
Mike Blumenkrantz
e303898258 zink: manually validate shaders in debug builds 
VVL is great, but there's actually cases where it doesn't catch critical
spirv errors, so add in our own validation pass to make sure things are
okay

this is especially useful for running on nvidia, as their compiler will
either crash on or silently drop illegal instructions

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16462>
 2022-05-17 02:55:20 +00:00
Mike Blumenkrantz
5f83571f92 lavapipe: fix pipeline handling for dynamic render zs state with pipeline library 
this is slightly more nuanced: if this is ONLY a fragment state,
pDepthStencilState must exist, but if it's BOTH fragment and output,
then pDepthStencilState must only exist if zs attachment is used

Fixes: d4d5a7abba ("lavapipe: implement EXT_graphics_pipeline_library")

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16457>
 2022-05-17 02:44:01 +00:00
Mike Blumenkrantz
0b2d383316 lavapipe: ignore depth/stencil states if attachment is not present 
depth and stencil states should only be set if the corresponding attachment
is present, otherwise they should be ignored. this is different from
ignoring the entire VkPipelineDepthStencilStateCreateInfo struct, as
it's possible that only depth or only stencil may be present

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16457>
 2022-05-17 02:44:01 +00:00
Timothy Arceri
77392e4983 vc4: disable GLSL IR loop unrolling 
NIR loop unrolling is already enabled so just let it do its job.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Timothy Arceri
b84e003079 r600: switch to NIR loop unrolling 
Note the NIR unrolling code was already enabled but we bump the
iteration unroll count to match the GLSL IR limit as per the
comment about loop bugs.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Timothy Arceri
dc2edb8f1d r300: disable GLSL IR loop unrolling 
NIR loop unrolling is already enabled so just let it do its job.

Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Timothy Arceri
1663b04592 i915g: switch to NIR loop unrolling 
Shader-db stats:

total instructions in shared programs: 406749 -> 406890 (0.03%)
instructions in affected programs: 216 -> 357 (65.28%)
total tex_indirect in shared programs: 12666 -> 12671 (0.04%)
tex_indirect in affected programs: 29 -> 34 (17.24%)
total temps in shared programs: 23447 -> 23451 (0.02%)
temps in affected programs: 296 -> 300 (1.35%)
total const in shared programs: 59400 -> 59455 (0.09%)
const in affected programs: 50 -> 105 (110.00%)
LOST:   0
GAINED: 17

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Timothy Arceri
11637f516c etnaviv: switch to NIR loop unrolling 
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Timothy Arceri
2a2a2e58d1 d3d12: switch to NIR loop unrolling 
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Timothy Arceri
c4295816af asahi: switch to NIR loop unrolling 
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Timothy Arceri
3ceaf589d6 softpipe: switch to NIR loop unrolling 
shader-db results:

total instructions in shared programs: 2788746 -> 2788886 (<.01%)
instructions in affected programs: 2126 -> 2266 (6.59%)
total loops in shared programs: 1357 -> 892 (-34.27%)
loops in affected programs: 468 -> 3 (-99.36%)
total temps in shared programs: 288754 -> 288725 (-0.01%)
temps in affected programs: 1623 -> 1594 (-1.79%)
total const in shared programs: 1954525 -> 1954621 (<.01%)
const in affected programs: 207 -> 303 (46.38%)
total imm in shared programs: 101023 -> 100891 (-0.13%)
imm in affected programs: 198 -> 66 (-66.67%)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Timothy Arceri
643774cdab i915g: use a valid setting for force_indirect_unrolling 
Otherwise we can hit asserts for example nir_deref_mode_must_be()
asserts on !(modes & ~nir_var_all)

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Timothy Arceri
d7a071a28f gallium/drivers: set force_indirect_unrolling_sampler for all required drivers 
This is set to true for all drivers that have a GLSL level
of support lower than 4.00. This matches the rule for setting the
GLSL IR option EmitNoIndirectSampler.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16543>
 2022-05-17 02:12:21 +00:00
Yonggang Luo
9baaf055e2 llvmpipe: Do not use _Atomic keyword that doesn't support by MSVC 
Fixes: 3269d34b29 ("llvmpipe/fence: make the fence id counter atomic")

Fixes:
```
../mesa/src/gallium/drivers/llvmpipe/lp_fence.c
../mesa/src/gallium/drivers/llvmpipe/lp_fence.c(47): error C2143: syntax error: missing ';' before 'type'
```

fence_id initialized to 0

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
 2022-05-16 18:57:06 +00:00
Marek Olšák
3382af7f6a radeonsi/gfx11: set BIG_PAGE for the attribute ring 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:41 -04:00
Marek Olšák
8a2f151ef8 radeonsi: print an error when failing to create a context 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:41 -04:00
Marek Olšák
6515b3b2dc radeonsi: fix a crash when failing to create a context 
When shader_query_buffers is NULL, the code treated as as non-empty.

Fixes: 792a638b03 "radeonsi/gfx10: implement streamout-related queries"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:40 -04:00
Marek Olšák
0755d02456 radeonsi: use AMDGPU_VM_PAGE_NOALLOC to disable MALL (infinity cache) 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:39 -04:00
Marek Olšák
e9e9086b66 radeonsi: use the new flag AMDGPU_GEM_CREATE_DISCARDABLE 
It forces the best placement (usually VRAM) and evictions discard the contents
instead of copying.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:39 -04:00
Marek Olšák
527e22412a winsys/amdgpu-radeon: clean up code related to heaps 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:38 -04:00
Marek Olšák
ac0becc648 radeonsi: use PIPE_RESOURCE_FLAG_UNMAPPABLE and DRIVER_INTERNAL more 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:38 -04:00
Marek Olšák
d21be64b3a winsys/amdgpu: handle RADEON_FLAG_ENCRYPTED as a heap modifier 
so that we don't need custom code for encrypted allocations

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:37 -04:00
Marek Olšák
593f72aa21 winsys/amdgpu-radeon: rework how we describe heaps 
It was getting difficult to add more heaps.

This adds more heaps because more flag combinations are legal now.
Invalid flag combinations are also handled better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:37 -04:00
Marek Olšák
ceddd7d49a radeonsi: rename RADEON_FLAG_UNCACHED -> RADEON_FLAG_GL2_BYPASS 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
 2022-05-16 07:03:36 -04:00
David Heidelberg
875643feeb ci: uprev piglit 2022-05-10 
Also document additional piglit failures and crashes with new tests.

Multiple changes, mostly notable:
 - few new tests
 - traces downloader improvements

Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16428>
 2022-05-16 06:33:36 +00:00
Kyle Russell
aa29e0d858 etnaviv: don't halve max_instructions for GC400 
This allows glamor to successfully compile its shaders on the GC400.

When running glamor using the GC400, Xorg reports that the compiled
shaders exceed the maximum allowed instructions because the value
reported from the kernel is halved.

Xserver[314]: etna_draw_vbo:318: compiled shaders are not okay

$ cat /sys/kernel/debug/dri/128/gpu | grep instruction_count
         instruction_count: 256

However, the spec for the Unified vertex-fragment shader explicitly
lists 256 as the maximum number of instructions for each shader
("256 for vertex shaders; 256 for fragment shaders").

Signed-off-by: Kyle Russell <bkylerussell@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16383>
 2022-05-16 05:53:05 +00:00
Timothy Arceri
7647023f3b glsl: enable the use of the nir based varying linker 
Here as well as calling the pass we need to switch the order of
some of the information gathering and optimisation calls. We also
need to create a custom callback for the dead variables removal
pass to clean up dead builtin varying in SSO programs without
causing piglit regressions.

shader-db results IRIS (BDW):

total instructions in shared programs: 17487900 -> 17477072 (-0.06%)
instructions in affected programs: 128682 -> 117854 (-8.41%)
helped: 587
HURT: 82
helped stats (abs) min: 1 max: 145 x̄: 18.82 x̃: 20
helped stats (rel) min: 0.21% max: 77.78% x̄: 17.41% x̃: 8.85%
HURT stats (abs)   min: 1 max: 6 x̄: 2.68 x̃: 2
HURT stats (rel)   min: 0.25% max: 9.76% x̄: 2.94% x̃: 2.16%
95% mean confidence interval for instructions value: -17.71 -14.66
95% mean confidence interval for instructions %-change: -16.40% -13.42%
Instructions are helped.

total cycles in shared programs: 857442520 -> 857170199 (-0.03%)
cycles in affected programs: 112252720 -> 111980399 (-0.24%)
helped: 13733
HURT: 13349
helped stats (abs) min: 1 max: 7293 x̄: 81.44 x̃: 10
helped stats (rel) min: <.01% max: 90.32% x̄: 3.30% x̃: 0.62%
HURT stats (abs)   min: 1 max: 7424 x̄: 63.38 x̃: 8
HURT stats (rel)   min: <.01% max: 192.23% x̄: 3.28% x̃: 0.54%
95% mean confidence interval for cycles value: -14.01 -6.10
95% mean confidence interval for cycles %-change: -0.17% 0.06%
Inconclusive result (%-change mean confidence interval includes 0).

total sends in shared programs: 971443 -> 970010 (-0.15%)
sends in affected programs: 4596 -> 3163 (-31.18%)
helped: 446
HURT: 39
helped stats (abs) min: 1 max: 6 x̄: 3.40 x̃: 4
helped stats (rel) min: 3.03% max: 85.71% x̄: 46.48% x̃: 50.00%
HURT stats (abs)   min: 1 max: 3 x̄: 2.15 x̃: 2
HURT stats (rel)   min: 6.67% max: 25.00% x̄: 15.16% x̃: 10.53%
95% mean confidence interval for sends value: -3.13 -2.78
95% mean confidence interval for sends %-change: -44.16% -38.88%
Sends are helped.

LOST:   235
GAINED: 262

Shader-db results radeonsi (RX580):

169505 shaders in 102144 tests
Totals:
SGPRS: 7698832 -> 7696552 (-0.03 %)
VGPRS: 5547296 -> 5545280 (-0.04 %)
Spilled SGPRs: 14795 -> 14773 (-0.15 %)
Spilled VGPRs: 3782 -> 3782 (0.00 %)
Private memory VGPRs: 1152 -> 1152 (0.00 %)
Scratch size: 3872 -> 3872 (0.00 %) dwords per thread
Code Size: 162946528 -> 162895264 (-0.03 %) bytes
Max Waves: 2449334 -> 2449736 (0.02 %)

Totals from affected shaders:
SGPRS: 215024 -> 212744 (-1.06 %)
VGPRS: 151976 -> 149960 (-1.33 %)
Spilled SGPRs: 162 -> 140 (-13.58 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 5249916 -> 5198652 (-0.98 %) bytes
Max Waves: 54588 -> 54990 (0.74 %)

Panfrost trace checksum is updated as per discussion in:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/6343

Some virpipe tess shader piglit tests are added as failures to CI
these failures are not a regression but an uncovered existing bug
exposed due to the linker no longer sorting internally facing
shader interfaces in alphabetical order. See details in:
https://gitlab.freedesktop.org/mesa/mesa/-/issues/6481

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15731>
 2022-05-16 03:33:18 +00:00
Sidney Just
5fda0a996a zink: enable pipe cap for win32 external memory and fences 
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15504>
 2022-05-15 19:56:49 +00:00