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radeonsi: rename RADEON_FLAG_UNCACHED -> RADEON_FLAG_GL2_BYPASS

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16466>
This commit is contained in:
Marek Olšák 2022-05-10 17:00:07 -04:00
parent 5bc289c547
commit ceddd7d49a
6 changed files with 38 additions and 38 deletions
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8
src/gallium/drivers/radeonsi/si_buffer.c
View file

@ -141,11 +141,11 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
/* For higher throughput and lower latency over PCIe assuming sequential access.
* Only CP DMA and optimized compute benefit from this.
* GFX8 and older don't support RADEON_FLAG_UNCACHED.
* GFX8 and older don't support RADEON_FLAG_GL2_BYPASS.
*/
if (sscreen->info.gfx_level >= GFX9 &&
res->b.b.flags & SI_RESOURCE_FLAG_UNCACHED)
res->flags |= RADEON_FLAG_UNCACHED;
res->b.b.flags & SI_RESOURCE_FLAG_GL2_BYPASS)
res->flags |= RADEON_FLAG_GL2_BYPASS;
/* Set expected VRAM and GART usage for the buffer. */
res->memory_usage_kb = MAX2(1, size / 1024);
@ -446,7 +446,7 @@ static void *si_buffer_transfer_map(struct pipe_context *ctx, struct pipe_resour
assert(!(usage & (TC_TRANSFER_MAP_THREADED_UNSYNC | PIPE_MAP_THREAD_SAFE)));
staging = si_aligned_buffer_create(ctx->screen,
SI_RESOURCE_FLAG_UNCACHED | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
SI_RESOURCE_FLAG_GL2_BYPASS | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
PIPE_USAGE_STAGING,
box->width + (box->x % SI_MAP_BUFFER_ALIGNMENT), 256);
if (staging) {

2
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -145,7 +145,7 @@ extern "C" {
(((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
#define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x) \
(((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
#define SI_RESOURCE_FLAG_UNCACHED (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
#define SI_RESOURCE_FLAG_GL2_BYPASS (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
enum si_has_gs {
GS_OFF,

4
src/gallium/drivers/radeonsi/si_test_dma_perf.c
View file

@ -117,7 +117,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
continue;
}
/* SI_RESOURCE_FLAG_UNCACHED setting RADEON_FLAG_UNCACHED doesn't affect
/* SI_RESOURCE_FLAG_GL2_BYPASS setting RADEON_FLAG_GL2_BYPASS doesn't affect
* chips before gfx9.
*/
if (test_cs && cache_policy && sctx->gfx_level < GFX9)
@ -153,7 +153,7 @@ void si_test_dma_perf(struct si_screen *sscreen)
enum pipe_resource_usage dst_usage, src_usage;
struct pipe_resource *dst, *src;
unsigned query_type = PIPE_QUERY_TIME_ELAPSED;
unsigned flags = cache_policy == L2_BYPASS ? SI_RESOURCE_FLAG_UNCACHED : 0;
unsigned flags = cache_policy == L2_BYPASS ? SI_RESOURCE_FLAG_GL2_BYPASS : 0;
if (placement == 0 || placement == 2 || placement == 4)
dst_usage = PIPE_USAGE_DEFAULT;

2
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -1025,7 +1025,7 @@ static struct si_texture *si_texture_create_object(struct pipe_screen *screen,
if (base->flags & PIPE_RESOURCE_FLAG_SPARSE)
resource->b.b.flags |= PIPE_RESOURCE_FLAG_UNMAPPABLE;
if (base->bind & PIPE_BIND_PRIME_BLIT_DST)
resource->b.b.flags |= SI_RESOURCE_FLAG_UNCACHED;
resource->b.b.flags |= SI_RESOURCE_FLAG_GL2_BYPASS;
/* Create the backing buffer. */
si_init_resource_fields(sscreen, resource, alloc_size, alignment);

58
src/gallium/include/winsys/radeon_winsys.h
View file

@ -74,7 +74,7 @@ enum radeon_bo_flag
RADEON_FLAG_READ_ONLY = (1 << 5),
RADEON_FLAG_32BIT = (1 << 6),
RADEON_FLAG_ENCRYPTED = (1 << 7),
RADEON_FLAG_UNCACHED = (1 << 8), /* only gfx9 and newer */
RADEON_FLAG_GL2_BYPASS = (1 << 8), /* only gfx9 and newer */
RADEON_FLAG_DRIVER_INTERNAL = (1 << 9),
};
@ -720,11 +720,11 @@ enum radeon_heap
RADEON_HEAP_GTT_WC_READ_ONLY_32BIT,
RADEON_HEAP_GTT_WC_32BIT,
RADEON_HEAP_GTT,
RADEON_HEAP_GTT_UNCACHED_WC,
RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY,
RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT,
RADEON_HEAP_GTT_UNCACHED_WC_32BIT,
RADEON_HEAP_GTT_UNCACHED,
RADEON_HEAP_GTT_GL2_BYPASS_WC,
RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY,
RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY_32BIT,
RADEON_HEAP_GTT_GL2_BYPASS_WC_32BIT,
RADEON_HEAP_GTT_GL2_BYPASS,
RADEON_MAX_SLAB_HEAPS,
RADEON_MAX_CACHED_HEAPS = RADEON_MAX_SLAB_HEAPS,
};
@ -743,11 +743,11 @@ static inline enum radeon_bo_domain radeon_domain_from_heap(enum radeon_heap hea
case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_WC_32BIT:
case RADEON_HEAP_GTT:
case RADEON_HEAP_GTT_UNCACHED_WC:
case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY:
case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_UNCACHED_WC_32BIT:
case RADEON_HEAP_GTT_UNCACHED:
case RADEON_HEAP_GTT_GL2_BYPASS_WC:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_32BIT:
case RADEON_HEAP_GTT_GL2_BYPASS:
return RADEON_DOMAIN_GTT;
default:
assert(0);
@ -761,19 +761,19 @@ static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
switch (heap) {
case RADEON_HEAP_GTT:
case RADEON_HEAP_GTT_UNCACHED:
case RADEON_HEAP_GTT_GL2_BYPASS:
break;
default:
flags |= RADEON_FLAG_GTT_WC;
}
switch (heap) {
case RADEON_HEAP_GTT_UNCACHED_WC:
case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY:
case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_UNCACHED_WC_32BIT:
case RADEON_HEAP_GTT_UNCACHED:
flags |= RADEON_FLAG_UNCACHED;
case RADEON_HEAP_GTT_GL2_BYPASS_WC:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_32BIT:
case RADEON_HEAP_GTT_GL2_BYPASS:
flags |= RADEON_FLAG_GL2_BYPASS;
break;
default:
break;
@ -784,8 +784,8 @@ static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
case RADEON_HEAP_VRAM_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_WC_READ_ONLY:
case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY:
case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY_32BIT:
flags |= RADEON_FLAG_READ_ONLY;
break;
default:
@ -797,8 +797,8 @@ static inline unsigned radeon_flags_from_heap(enum radeon_heap heap)
case RADEON_HEAP_VRAM_32BIT:
case RADEON_HEAP_GTT_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_WC_32BIT:
case RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_UNCACHED_WC_32BIT:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY_32BIT:
case RADEON_HEAP_GTT_GL2_BYPASS_WC_32BIT:
flags |= RADEON_FLAG_32BIT;
FALLTHROUGH;
default:
@ -831,7 +831,7 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain, enum radeo
return -1;
/* Unsupported flags: NO_SUBALLOC, SPARSE. */
if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_UNCACHED |
if (flags & ~(RADEON_FLAG_GTT_WC | RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GL2_BYPASS |
RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT |
RADEON_FLAG_DRIVER_INTERNAL))
return -1;
@ -859,20 +859,20 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain, enum radeo
}
break;
case RADEON_DOMAIN_GTT:
uncached = flags & RADEON_FLAG_UNCACHED;
uncached = flags & RADEON_FLAG_GL2_BYPASS;
switch (flags & (RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT)) {
case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
return uncached ? RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY_32BIT
return uncached ? RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY_32BIT
: RADEON_HEAP_GTT_WC_READ_ONLY_32BIT;
case RADEON_FLAG_GTT_WC | RADEON_FLAG_READ_ONLY:
return uncached ? RADEON_HEAP_GTT_UNCACHED_WC_READ_ONLY
return uncached ? RADEON_HEAP_GTT_GL2_BYPASS_WC_READ_ONLY
: RADEON_HEAP_GTT_WC_READ_ONLY;
case RADEON_FLAG_GTT_WC | RADEON_FLAG_32BIT:
return uncached ? RADEON_HEAP_GTT_UNCACHED_WC_32BIT
return uncached ? RADEON_HEAP_GTT_GL2_BYPASS_WC_32BIT
: RADEON_HEAP_GTT_WC_32BIT;
case RADEON_FLAG_GTT_WC:
return uncached ? RADEON_HEAP_GTT_UNCACHED_WC : RADEON_HEAP_GTT_WC;
return uncached ? RADEON_HEAP_GTT_GL2_BYPASS_WC : RADEON_HEAP_GTT_WC;
case RADEON_FLAG_READ_ONLY | RADEON_FLAG_32BIT:
case RADEON_FLAG_READ_ONLY:
assert(!"READ_ONLY without WC is disallowed");
@ -881,7 +881,7 @@ static inline int radeon_get_heap_index(enum radeon_bo_domain domain, enum radeo
assert(!"32BIT without WC is disallowed");
return -1;
case 0:
return uncached ? RADEON_HEAP_GTT_UNCACHED : RADEON_HEAP_GTT;
return uncached ? RADEON_HEAP_GTT_GL2_BYPASS : RADEON_HEAP_GTT;
}
break;
default:

2
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
View file

@ -574,7 +574,7 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *ws,
if (!(flags & RADEON_FLAG_READ_ONLY))
vm_flags |= AMDGPU_VM_PAGE_WRITEABLE;
if (flags & RADEON_FLAG_UNCACHED)
if (flags & RADEON_FLAG_GL2_BYPASS)
vm_flags |= AMDGPU_VM_MTYPE_UC;
r = amdgpu_bo_va_op_raw(ws->dev, buf_handle, 0, size, va, vm_flags,