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radeonsi/gfx11: don't insert shader code for GS_PIPELINE_STATS_EMU

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GS_PIPELINE_STATS_EMU is always false, so the branches were never entered.

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
This commit is contained in:
Marek Olšák 2022-05-14 02:19:56 -04:00 • committed by Marge Bot
parent fcaa9f5096
commit a8d2ef8bd6
1 changed files with 42 additions and 38 deletions
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80
src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
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@ -1853,27 +1853,29 @@ void gfx10_ngg_gs_emit_begin(struct si_shader_context *ctx)
}
ac_build_endif(&ctx->ac, 5090);
tmp = si_is_gs_thread(ctx);
ac_build_ifcc(&ctx->ac, tmp, 15090);
{
tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1);
tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
ac_build_ifcc(&ctx->ac, tmp, 5109); /* if (GS_PIPELINE_STATS_EMU) */
LLVMValueRef args[] = {
ctx->ac.i32_1,
ngg_get_emulated_counters_buf(ctx),
LLVMConstInt(ctx->ac.i32,
(si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_INVOCATIONS) +
SI_QUERY_STATS_END_OFFSET_DW) * 4,
false),
ctx->ac.i32_0, /* soffset */
ctx->ac.i32_0, /* cachepolicy */
};
if (ctx->screen->info.gfx_level < GFX11) {
tmp = si_is_gs_thread(ctx);
ac_build_ifcc(&ctx->ac, tmp, 15090);
{
tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1);
tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
ac_build_ifcc(&ctx->ac, tmp, 5109); /* if (GS_PIPELINE_STATS_EMU) */
LLVMValueRef args[] = {
ctx->ac.i32_1,
ngg_get_emulated_counters_buf(ctx),
LLVMConstInt(ctx->ac.i32,
(si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_INVOCATIONS) +
SI_QUERY_STATS_END_OFFSET_DW) * 4,
false),
ctx->ac.i32_0, /* soffset */
ctx->ac.i32_0, /* cachepolicy */
};
ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0);
ac_build_endif(&ctx->ac, 5109);
}
ac_build_endif(&ctx->ac, 15090);
ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0);
ac_build_endif(&ctx->ac, 5109);
}
ac_build_endif(&ctx->ac, 15090);
}
ac_build_waitcnt(&ctx->ac, AC_WAIT_LGKM);
ac_build_s_barrier(&ctx->ac, ctx->stage);
@ -2183,26 +2185,28 @@ void gfx10_ngg_gs_build_end(struct si_shader_context *ctx)
ac_build_export_prim(&ctx->ac, &prim);
tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1);
tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
ac_build_ifcc(&ctx->ac, tmp, 5229); /* if (GS_PIPELINE_STATS_EMU) */
ac_build_ifcc(&ctx->ac, LLVMBuildNot(builder, prim.isnull, ""), 5237);
{
LLVMValueRef args[] = {
ctx->ac.i32_1,
ngg_get_emulated_counters_buf(ctx),
LLVMConstInt(ctx->ac.i32,
(si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_PRIMITIVES) +
SI_QUERY_STATS_END_OFFSET_DW) * 4,
false),
ctx->ac.i32_0, /* soffset */
ctx->ac.i32_0, /* cachepolicy */
};
if (ctx->screen->info.gfx_level < GFX11) {
tmp = si_unpack_param(ctx, ctx->vs_state_bits, 31, 1);
tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
ac_build_ifcc(&ctx->ac, tmp, 5229); /* if (GS_PIPELINE_STATS_EMU) */
ac_build_ifcc(&ctx->ac, LLVMBuildNot(builder, prim.isnull, ""), 5237);
{
LLVMValueRef args[] = {
ctx->ac.i32_1,
ngg_get_emulated_counters_buf(ctx),
LLVMConstInt(ctx->ac.i32,
(si_hw_query_dw_offset(PIPE_STAT_QUERY_GS_PRIMITIVES) +
SI_QUERY_STATS_END_OFFSET_DW) * 4,
false),
ctx->ac.i32_0, /* soffset */
ctx->ac.i32_0, /* cachepolicy */
};
ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0);
ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.raw.buffer.atomic.add.i32", ctx->ac.i32, args, 5, 0);
}
ac_build_endif(&ctx->ac, 5237);
ac_build_endif(&ctx->ac, 5229);
}
ac_build_endif(&ctx->ac, 5237);
ac_build_endif(&ctx->ac, 5229);
}
ac_build_endif(&ctx->ac, 5140);