Nicolai Hähnle
cb07f91489
amd/common: move ac_shader_{binary,reloc} into r600 and rename
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They are no longer used by radeonsi or radv.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-04 10:52:26 +00:00
Nicolai Hähnle
510e74ff48
amd/common: removed unused ac_shader_binary functions
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Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-04 10:52:26 +00:00
Nicolai Hähnle
b398230e6d
amd/common: remove unused ac_compile_module_to_binary
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Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
6a220e67ce
radv: Switch to using rtld.
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
5ff651c0a7
radv: Move more stuff to variant create time.
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Due to them depending on the linker result.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
726a31df70
radv: Add the concept of radv shader binaries.
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This simplifies a bunch of stuff by
(1) Keeping all the things in a single allocation, making things easier
for the cache.
(2) creating a shader_variant creation helper.
This is immediately put to use by creating rtld shader binaries. This
is the main reason for the binaries, as we need to do the linking at
upload time, i.e. post caching. We do not enable rtld yet.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
43f2f01cc8
radv: Add export_prim_id to the shader variant info.
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
15046ef7c8
radv: use last nir shader to determine stage in postprocessing
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Bas Nieuwenhuizen
7469516244
radv: Merge rsrc1/rsrc2 fields with the config fields.
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-04 10:52:26 +00:00
Samuel Pitoiset
cce2645810
radv: do not crash when generating binning state for unknown chips
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These values are only useful if binning is disabled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-04 12:22:46 +02:00
Samuel Pitoiset
8a425e057d
radv: fix potential crash in the compute resolve path
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If the destination attachment is UNUSED.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-04 12:22:43 +02:00
Tomeu Vizoso
0cc02c9ea6
panfrost: Take into account off-screen FBOs
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In that case, ctx->pipe_framebuffer.cbufs[0] can be NULL.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Boris Brezillon <boris.brezillon@collabora.com>
Fixes: 5375d009be ("panfrost: Pass referenced BOs to the SUBMIT ioctls")
2019-07-04 10:48:09 +02:00
Christian Gmeiner
f39a7fd627
util/macros: rework DIV_ROUND_UP macro
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Simplify used math.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
2019-07-04 10:21:32 +02:00
Kenneth Graunke
9ea67f0a79
iris: Fix MOCS for grid surface
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Hardcoding 4 is bad; we have a function for this now.
2019-07-03 22:24:50 -07:00
Kenneth Graunke
10560f8506
iris: Minor tidying
2019-07-03 22:24:44 -07:00
Marek Olšák
6ab23805c3
Revert "mesa/st: Passthrough scissor when clearing by quad"
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This reverts commit 0a88aa3025 .
It breaks a lot of piglit tests.
2019-07-04 01:08:02 -04:00
Marek Olšák
8dfdf5aae4
gallium/u_blitter: add return to fix the build
2019-07-03 23:44:14 -04:00
Alyssa Rosenzweig
0a88aa3025
mesa/st: Passthrough scissor when clearing by quad
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The scissor state -is- setup, but the scissor test is not enabled. This
can prevent certain optimizations from occurring on tilers where
unaffected tiles are thrown out entirely.
v2: Only enable scissor test if the scissor test is actually set by the
app, to avoid regressing quad-based clears used for other reasons (like
a color mask).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-07-03 14:33:46 -07:00
Marek Olšák
92e34568b7
radeonsi/gfx10: fix legacy GS
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LLVM doesn't insert s_waitcnt_vscnt before GS_DONE.
There was also the crash in legacy GS copy shader.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Nicolai Hähnle
dfa8e758c2
radeonsi/gfx10: disable clear state
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Nicolai Hähnle
0dd57f0fc0
radeonsi/gfx10: disable DPBB
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Nicolai Hähnle
815fd77a47
radeonsi/gfx10: disable SDMA
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
f66ee5af2f
radeonsi: determine the rasterization primitive type accurately (v2)
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v2: reworked version to fix bugs and make it more efficient
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
a4b3eea325
radeonsi/gfx10: consolidate & improve input_prim determination for NGG
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
969e5176c2
ac: rework ac_build_waitcnt for gfx10
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
214ddfb688
radeonsi/gfx10: implement si_shader_vs
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Only used with tessellation + GS instancing.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
6cf2fb1fc4
radeonsi/gfx10: unpack GS invocation ID
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
32694456f7
radeonsi/gfx10: jump over the shader query atomic if the queries are disabled
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
244a8e6798
radeonsi/gfx10: cosmetic changes
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
09a905d930
radeonsi/gfx10: set cache control registers
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
b680f723f8
radeonsi/gfx10: export correct PrimitiveID from NGG vertex shaders
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
3203a74dcb
radeonsi/gfx10: set PA_SC_TILE_STEERING_OVERRIDE
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
07aacdbfd5
radeonsi/gfx10: add a workaround for stencil HTILE with mipmapping
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
51db950419
radeonsi/gfx10: disable DCC with MSAA
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It was only enabled for 2x MSAA anyway.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
6920f09f4b
radeonsi/gfx10: fix GL_LINE polygon mode for decomposed primitives
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We need to tell PA to accept edge flags generated by the input assembler,
because decomposed primitives shouldn't draw inner edges.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
e39d4594da
radeonsi/gfx10: fix NGG GS color clamping
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Just need to pass the input from ES to GS. Everything else is done.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
40e7c65590
radeonsi/gfx10: fix vertex color clamping for TES
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
cc7875150a
radeonsi/gfx10: unbind NGG shaders when destroyed
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This fixes glsl-max-varyings, which creates shaders, draws, and then
destroys them.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
b90ddff477
radeonsi/gfx10: don't use the GS workaround for triangle strips w/ adjancency
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
c3ac22a620
radeonsi/gfx10: don't do the query buffer atomic for blit shaders
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
adbec817d3
radeonsi/gfx10: update spi_map if API VS (as NGG) changes and PS doesn't
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
1e39c21c23
radeonsi/gfx10: fix a possible hang with exp pos0 with done=0 and exec=0
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
683cf11b81
radeonsi/gfx10: prefetch HW GS when NGG is used
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Nicolai Hähnle
76898a8062
amd/common/gfx10: set DLC for llvm.amdgcn.s.buffer.load
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
7f71579064
radeonsi/gfx10: fix PS exports for SPI_SHADER_32_AR
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
4bdf44724f
radeonsi/gfx10: set DLC for loads when GLC is set
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This fixes L1 shader array cache coherency.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
f81aa6b0c8
radeonsi/gfx10: fix shader images
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Don't promote 2D image instructions to 3D, and don't set z=BASE_ARRAY.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
7c805a7c67
radeonsi/gfx10: set the DCC constant encoding flag
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
6eb219e963
radeonsi/gfx10: fix intensity formats
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move the ALPHA_IS_ON_MSB fixup into vi_alpha_is_on_msb
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
6944f99176
radeonsi/gfx10: allocate GDS BOs for streamout
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00