Commit graph

187012 commits

Author SHA1 Message Date
Alyssa Rosenzweig
351698d165 asahi: be robust against tess batch changes
fixes faults in arb_shader_image_load_store-coherency

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
20089a681a asahi: implement CDM stream linking for GS
fixes crash with massive #s of geometry shader draws, as seen in
arb_shader_image_load_store-coherency

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
69dc5bed89 asahi: fix depth bias interactions with points/lines
we need to apply depth bias for tris with point/line poly mode (according to
offset_point/offset_line), but we need to NOT apply depth bias for API-level
points/lines. weirdly the hw is sensitive to that last part.

fixes z-fighting with FreeCAD.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
2c40768207 asahi: accelerate QBO copies
using a compute shader to avoid a stall.

doubles/triples perf in smo metro in ryu

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
6f642e9bb9 asahi: add helper to classify queries
to share query/qbo code

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
7bc904cb4a asahi: add flush_query_writers helper
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
c0582fcd8e asahi: export build_meta_shader
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
83737cca5c asahi: fix stage accounting for meta compute shaders
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
f2a1d38096 asahi: fix unit mismatch with unroll path
Fixes GS line/point expansion in Dolphin, as well as corruption in Blender when
the dancing ants show up

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
1dee26b61f asahi: zero more in the unroll path
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
2f1b50d8bc asahi: clarify how unroll index buffers are offsetted
it's a little inconsistent

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
e952189443 asahi: fix overread with samplers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
007a440a33 asahi/lib: fix overread with stateful
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
0a8d0217c9 asahi: move more code out of agx_preprocess_nir
we need to gather tex masks  / lower mediump io before lowering textures for our
detection to work ... also we want driver-side i/o soon lowering for Marek's
thing anyway. do some code motion / pass reordering to make this doable.

in doing so, we get rid of agx_uncompiled_shader_info which is probably good.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
d6800d5cc6 asahi: allow more samplers for shaderdb
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Isaac Marovitz
ff6722814a asahi: Add >16 Sampler Access for Ryujinx
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Alyssa Rosenzweig
4779e9d574 asahi: bump maximum samplers for Blender
Blender needs more samplers to render the "wanderer" scene. While our binding
table is limited, we can get additional samplers by downshifting to the bindless
sampler heap, at a performance penalty. That mechanism is already in place for
merged VS/TCS, so we can reuse it for this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483>
2024-03-30 00:26:17 +00:00
Faith Ekstrand
0e4b5e0b00 nil: Drop unneeded types from formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28453>
2024-03-30 00:03:46 +00:00
Faith Ekstrand
4c59398615 nil: Remove 2-bit SNORM from the format table
Initially I left it in place because I didn't want to disturb the table
beyond what was in nv50_formats.c.  However, we've moved past that now
and these formats are permanently broken so it's easiest to just remove
them from the table rather than have them in the table and then have C
code which disables them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28453>
2024-03-30 00:03:46 +00:00
Faith Ekstrand
4ca6ad7f8c nil: Drop bogus color formats from non-renderable luminance/alpha formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28453>
2024-03-30 00:03:46 +00:00
Faith Ekstrand
7b6b5aa0c6 nil: Switch to using the CSV generated table
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28453>
2024-03-30 00:03:45 +00:00
Faith Ekstrand
bc0ce3848f nil: Re-organize the format table
For normal color formats, sort them by largest component size then by
number of components.  This should make things easier to find.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28453>
2024-03-30 00:03:45 +00:00
Faith Ekstrand
70843be321 nil: Add a CSV version of the format table
This is much more readable than the macro mess we had before.  Most
notably because we no longer have this mess of #defines for format
support flags and instead have a character per flag and every every
supported flag is there every time.  This makes it way easier to figure
out what we're actually claiming a format can do.

This conversion was tested with a patch that did a memcmp() of this
table against the old one to ensure that the two tables are bit-for-bit
identical.  Later commits may modify the table in various ways but this
conversion to a CSV file is lossless.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28453>
2024-03-30 00:03:45 +00:00
Faith Ekstrand
3f50d72ec5 nak: Don't do a scope break cascade for nir_jump_halt
Fixes: 9312356d99 ("nak/nir: Add a control-flow lowering pass")
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28456>
2024-03-29 23:08:50 +00:00
Faith Ekstrand
b593de2c49 nir: Delete the rest of the CF list when adding a halt
In nir_lower_terminate_to_demote(), we were deleting the rest of the
block contents when we added a halt instruction but left any subsequent
CF nodes in the list.  While this may be technically okay, that much
dead code makes the rest of NIR pretty grumpy.  It's better to delete
everything to the end of the CF list, not just everything to the end of
the block.

Fixes: 75861c64b8 ("nir: Add a lower_terminate_to_demote pass")
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28456>
2024-03-29 23:08:50 +00:00
Caio Oliveira
d9e737212d intel/brw: Add a src array for the common case in fs_inst
In the common case, fs_inst will have up to 4 sources (the HW
instructions have up to 3, and our representation of SENDs have 4).
Embed such array into the fs_inst, and use it whenever applicable
instead of allocating a new array.

Also change the code to reuse the allocated src array when resizing to
a smaller length.

Between the changes above and the reduced amount of initializing
fs_regs, this reduces fossil-db time by around 2% for Borderlands 3
and Rise of the Tomb Raider, and around 1.5% for Total War Warhammer 3.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28379>
2024-03-29 22:44:01 +00:00
Caio Oliveira
dae9795628 intel/brw: Remove vestiges of sources on IF opcode, only valid on Gfx6
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28379>
2024-03-29 22:44:01 +00:00
Kenneth Graunke
816a33849a intel/brw: Rearrange fs_inst fields
For better packing, and to make all the small fields easier to hash
and compare en masse.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28379>
2024-03-29 22:44:01 +00:00
Eric Engestrom
814017103c rpi/ci: another batch of flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28481>
2024-03-29 22:22:21 +00:00
Faith Ekstrand
6f395d44b1 nvk: Advertise VK_KHR_maintenance6
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27796>
2024-03-29 22:03:25 +00:00
Valentine Burley
16397c10c7 nvk: Add support for version 2 of all descriptor binding commands
Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27796>
2024-03-29 22:03:25 +00:00
Faith Ekstrand
3a88e3f18b nvk: Support VkBindMemoryStatusKHR
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27796>
2024-03-29 22:03:25 +00:00
Ian Romanick
5e9c01dfe4 intel/brw/xe2+: Use phys_nr and phys_subnr in DPAS encoding
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404>
2024-03-29 21:12:32 +00:00
Ian Romanick
6d85f7129a intel/brw/xe2+: DPAS must be SIMD16 now
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404>
2024-03-29 21:12:32 +00:00
Ian Romanick
a8115221e5 nir: intel/brw: Change the order of sources for nir_dpas_intel
It was by pure luck that all sources (and the result) of nir_dpas_intel
had the same number of components. It is possible to support matrix
sizes where the accumlator matrix and the result matrix are larger
(e.g., 16x8 * 8x16 = 16x16).

This breaks all of the assumptions of NIR's infrastructure for code
generating intrinsics. Fix the by making the accumulator matrix be the
first source. The accumulator and the result will always have the same
dimensions (due to rules of matrix multiplication) and the same type
(due to restructions of the cooperative matrix extension). This forces
them to have the same number of components.

This doesn't fix all the potential problems. NIR expects that all
0-sized sources will have the same number of components. This just
ensures that the result has the correct number of components.

Fixes: 6b14da33ad ("intel/fs: nir: Add nir_intrinsic_dpas_intel")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404>
2024-03-29 21:12:32 +00:00
Ian Romanick
c6bd6f2a41 intel/brw: Use enums for DPAS source regioning
Was previously passing 1, 1, 0 as the regioning. This generated
incorrect disassembly because the encoding for a width of 1 is 0. Use
the enums to ensure the correct values are used.

Fixes: 1c92dad5cb ("intel/disasm: Disassembly support for DPAS")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404>
2024-03-29 21:12:32 +00:00
Ian Romanick
be4fa59a72 intel/brw: Clear write_accumulator flag when changing the destination
If the destination was the accumulator but is no longer, having the flag
set is not correct. On Xe2 this also causes a validation error.

v2: Reword the comment to be more clear. Suggested by Jordan.

Fixes: efa4e4bc5f ("intel/fs: Introduce regioning lowering pass.")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28404>
2024-03-29 21:12:32 +00:00
Faith Ekstrand
b5f4b16811 nak: Implement load_ubo with an indirect cbuf index
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28474>
2024-03-29 19:30:16 +00:00
Faith Ekstrand
f4ac517cc8 nak: Plumb through LDC modes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28474>
2024-03-29 19:30:16 +00:00
Eric Engestrom
189b4193ee ci_run_n_monitor: explain how to pass multiple targets without having to use regexes
Fixes: 6825c67c99 ("ci_run_n_monitor: allow passing multiple targets")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28461>
2024-03-29 19:23:24 +00:00
Eric Engestrom
48566d00b1 ci: don't run rustfmt on every core change
Only keep the two parts we want: disabling the job in the nightly
pipeline, and running the job if the CI itself is modified.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28468>
2024-03-29 18:43:38 +00:00
Jesse Natalie
4f310b04f0 wgl: The default swap interval is supposed to be 1
Per WGL_EXT_swap_control:
> The default swap interval is 1.

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28471>
2024-03-29 17:29:18 +00:00
Eric Engestrom
cc5e9def56 radv/ci: dEQP-VK.spirv_assembly.type.vec4.i8.mod_geom Fail -> Crash on tahiti
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28472>
2024-03-29 16:36:10 +00:00
Eric Engestrom
64293c5aa3 radv/ci: another batch of flakes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28472>
2024-03-29 16:36:10 +00:00
Mike Blumenkrantz
edeb3fec4d zink: only check that CUBE_COMPATIBLE for images doesn't subtract flags
the flags may change if e.g., HOST_TRANSFER is enabled by adding CUBE

fixes #10924

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28460>
2024-03-29 13:09:40 +00:00
Rhys Perry
03938804f1 aco: avoid breaking clauses with waitcnt
fossil-db (navi31):
Totals from 3573 (4.50% of 79395) affected shaders:
Instrs: 6172096 -> 6170009 (-0.03%); split: -0.04%, +0.01%
CodeSize: 31448052 -> 31439660 (-0.03%); split: -0.03%, +0.01%
Latency: 37317302 -> 37307935 (-0.03%); split: -0.03%, +0.00%
InvThroughput: 6820967 -> 6819930 (-0.02%); split: -0.02%, +0.00%
VClause: 163424 -> 157705 (-3.50%)
SClause: 135441 -> 135295 (-0.11%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28433>
2024-03-29 12:04:13 +00:00
Karol Herbst
88a9576a3e meson: fix link failure with llvm-18
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10739
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10775
cc: mesa-stable

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28267>
2024-03-29 07:31:02 +00:00
Timur Kristóf
3fd002f6d5 radv, aco: Remove the code that jumped to RADV's TCS epilogs.
The actual TCS epilog selection code is kept unchanged for now,
we'll delete it when RadeonSI also gets rid of TCS epilogs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
2024-03-28 23:44:03 +00:00
Timur Kristóf
e421923692 radv: Completely delete TCS epilogs.
TCS epilogs are not needed anymore because the TCS can implement
dynamic states by itself now.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
2024-03-28 23:44:03 +00:00
Timur Kristóf
508f293b14 ac/nir/tess: Emit tess factor stores based on new intrinsics.
This allows the TCS to read the primitive mode and whether
TES reads the tess factors, from an SGPR arg, which lets it
decide how to store them at runtime.

For linked shaders, the conditions will be constant and
NIR optimizations can delete the dead CF.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28408>
2024-03-28 23:44:03 +00:00