Commit graph

64451 commits

Author SHA1 Message Date
Jason Ekstrand
34ee3f5a34 docs/GL3: Mark ARB_copy_image as implemented on i965 2014-08-11 11:26:14 -07:00
Jason Ekstrand
410fea8dd9 i965: Add support for ARB_copy_image
This, together with the meta path, provides a complete implemetation of
ARB_copy_image.

v2: Add a fallback memcpy path for when the texture is too big for the
    blitter
v3: Properly support copying between two places on the same texture in the
    memcpy fallback
v4: Properly handle blit between the same two images in the fallback path
v5: Properly handle blit between the same two compressed images in the
    fallback path
v6: Fix a typo in a comment

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
2014-08-11 11:26:14 -07:00
Jason Ekstrand
8ad7c1903d mesa/meta: Add a partial implementation of CopyImageSubData
This provides an implementation of CopyImageSubData that works if both
textures are uncompressed.  This implementation works by using a
combination of texture views and BlitFramebuffer.  If one of the textures
is compressed, it returns false and the driver is expected to provide a
fallback.

v2: Don't leak fbo's

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

v3: Change glGen/DeleteTextures to _mesa_Gen/DeleteTextures
2014-08-11 11:26:00 -07:00
Jason Ekstrand
80a8b020c0 mesa/meta: Make _mesa_meta_bind_fbo_image also take a framebuffer target
Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
2014-08-11 11:20:23 -07:00
Jason Ekstrand
41b6460e08 mesa: Add GL API support for ARB_copy_image
This adds the API entrypoint, error checking logic, and a driver hook for
the ARB_copy_image extension.

v2: Fix a typo in ARB_copy_image.xml and add it to the makefile
v3: Put ARB_copy_image.xml in the right place alphebetically in the
    makefile and properly prefix the commit message
v4: Fixed some line wrapping and added a check for null
v5: Check for incomplete renderbuffers

Signed-off-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Reviewed-by: Neil Roberts <neil@linux.intel.com>

v6: Update dispatch_sanity for the addition of CopyImageSubData
2014-08-11 11:20:23 -07:00
Matt Turner
23d782067a i965/fs: Keep track of the register that hold delta_x/delta_y.
They're needed in register allocation. Fixes a regression since
afe3d155.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78875
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-11 10:40:01 -07:00
Matt Turner
41bdad59ab i965: Mark branch unreachable in sampler state code.
Silences some uninitialized variable warnings.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-11 10:40:01 -07:00
Brian Paul
904ed3b315 mesa: simplify _mesa_update_draw_buffers()
There's no need to copy the array of DrawBuffer enums to a temp array.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-11 09:44:51 -06:00
Brian Paul
39b40ad144 mesa: fix assertion in _mesa_drawbuffers()
Fixes failed assertion when _mesa_update_draw_buffers() was called
with GL_DRAW_BUFFER == GL_FRONT_AND_BACK.  The piglit gl30basic hit
this.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-11 09:44:51 -06:00
Brian Paul
dd8f15a553 mesa: whitespace, 80-column wrapping in program.c
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-11 09:44:50 -06:00
Brian Paul
d8f7577d5f mesa: simplify/rename _mesa_init_program_struct()
No need to return a value.  Remove unused ctx parameter.  Remove
_mesa_ prefix since it's static.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-11 09:44:50 -06:00
Brian Paul
53b13b2ead st/mesa: use PRId64 for printing 64-bit ints
v2: use signed types/formats

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-11 09:44:50 -06:00
Brian Paul
80fa7fd23e mesa: use PRId64 for printing 64-bit ints
Silences MinGW warnings:
 warning: unknown conversion type character ‘l’ in format [-Wformat]
 warning: too many arguments for format [-Wformat-extra-args]

v2: use signed types/formats

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-11 09:44:44 -06:00
Brian Paul
a5743fdf7d mesa: define and use ALL_TYPE_BITS in varray.c code
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-11 09:37:50 -06:00
Brian Paul
288f887622 mesa: add comment that GL_CLIP_DISTANCE0 == GL_CLIP_PLANE0 in enable.c
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-08-11 09:37:50 -06:00
Maarten Lankhorst
4c16e6a8e0 configure.ac: Do not require llvm on x32
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Maarten Lankhorst <dev@mblankhorst.nl>
2014-08-11 13:16:11 +02:00
Neil Roberts
1b417ea784 i965: Don't check for format differences when using the blorp blitter
Previously the blorp blitter wouldn't be used if the source and destination
buffer had a different format other than swizzling between RGB and BGR and
adding or removing a dummy alpha channel. However there's no reason why the
blorp code path can't be used to do almost all format conversions so this
patch just removes the checks. However it does explicitly disable converting
to/from MESA_FORMAT_Z24_UNORM_X8_UINT because there is a similar check
brw_blorp_copytexsubimage.

This doesn't cause any Piglit test regressions at least on Ivybridge.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-11 11:24:46 +01:00
Kenneth Graunke
9276ef6f41 i965/eu: Allow math on immediates on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
db64c2eee2 i965/eu: Update jump distance scaling for Broadwell.
Broadwell measures jump distances in bytes, so we need to scale by 16.

v2: Update the function in brw_eu.h, not in brw_eu_emit.c.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
82ddd517af i965/eu: Refactor jump distance scaling to use a helper function.
Different generations of hardware measure jump distances in different
units.  Previously, every function that needed to set a jump target open
coded this scaling, or made a hardcoded assumption (i.e. just used 2).

Most functions start with the number of instructions to jump, and scale
up to the hardware-specific value.  So, I made the function match that.

Others start with a byte offset, and divide by a constant (8) to obtain
the jump distance.  This is actually 16 / 2 (the jump scale for Gen5-7).

v2: Make the helper a static inline defined in brw_eu.h, instead of
    an actual function in brw_eu_emit.c (as suggested by Matt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
a1c899c718 i965/eu: Set UIP on ELSE instructions on Broadwell.
Broadwell adds UIP on ELSE instructions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
7d41170b62 i965/eu: Make it clear that brw_patch_break_count only runs on Gen4-5.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
0457464c33 i965/eu: Make it clear that brw_find_loop_end only runs on Gen6+.
It has Gen6+ knowledge baked in, and indeed is only called for Gen6+,
but it wasn't immediately obvious that this was the case.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
0d6adce469 i965/eu: Port Broadwell CMP destination type hack to brw_eu_emit.c.
See gen8_generator::CMP().

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:34 -07:00
Kenneth Graunke
49519a1b63 i965/eu: Explicitly disable instruction compaction on Broadwell for now.
Until now, it's been off implicitly: we never call the compactor
function.  When we merge the generators, we'll start calling it, so we
should make it do nothing.

Matt will enable instruction compaction properly later.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:32:33 -07:00
Kenneth Graunke
8609df97a0 i965/eu: Use Haswell atomic messages on Broadwell.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:03:45 -07:00
Kenneth Graunke
e1bd2ca28a i965/eu: Change gen == 7 to gen >= 7 in a couple brw_eu_emit.c cases.
Broadwell is going to use the brw_eu_emit.c code soon.  We want to get
the fake MRF handling and URB HWord channel mask handling.

We don't need the CMP thread switch workaround, though.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-10 19:01:52 -07:00
Ben Widawsky
38e181bad2 i965/clip: Removing scissor atom
Now that we no longer use ctx->DrawBuffer->_Xmin and related fields to
program the screen-space viewport extents, we don't depend on any
scissoring state.  So we can drop the +_NEW_SCISSOR dependency.

On GEN8, a change in scissor state does not effect anything for the
clipper/sf hardware state. The hardware will always do the right thing
once the viewport extents are programmed. We can therefore remove the
unecessary state emission.

Ken originally spotted this.

v2: Reword the commit message. Remove spurious hunk.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 17:13:36 -07:00
Ben Widawsky
f6725d627c i965/guardband: Enable for all viewport dimensions (GEN8+)
The goal of guardband clipping is to try to avoid 3d clipping because it
is an expensive operation. When guardband clipping is disabled, all
geometry that intersects the viewport is sent to the FF 3d clipper.
Objects which are entirely enclosed within the viewport are said to be
"trivially accepted" while those entirely outside of the viewport are,
"trivially rejected".

When guardband clipping is turned on the above behavior is changed such
that if the geometry is within the guardband, and intersects the
viewport, it skips the 3d clipper. Prior to GEN8, this was problematic
if the viewport was smaller than the screen as it could allow for
rendering to occur outside of the viewport. That could be mitigated if
the programmer specified a scissor region which was less than or equal
to the viewport - but this is not required for correctness in OpenGL. In
theory you could be clever with the guardband so as not to invoke this
problem. We do not do this, and have no data that suggests we should
bother (nor the converse data).

With viewport extents in place on GEN8, it should be safe to turn on
guardband clipping for all cases

While here, add a comment to the code which confused me thoroughly.

v2: Update grammar in commit message. Reword comments based on Ken's
suggestion.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 17:13:36 -07:00
Ben Widawsky
1a20e38ccf i965: Simplify viewport extents programming on GEN8
Viewport extents are a 3rd rectangle that defines which pixels get
discarded as part of the rasterization process. The actual pixels drawn
to the screen are an intersection of the drawing rectangle, the viewport
extents, and the scissor rectangle. It permits the use of guardband
clipping in all cases (see later patch). The actual pixels drawn to the
screen are an intersection of the drawing rectangle, the viewport
extents, and the scissor rectangle.

Scissor rectangle is not super important for this discussion as it should
always help do the right thing provided the programmer uses it.

switch (viewport dimensions, drawrect dimension) {
   case viewport > drawing rectangle: no effects; break;
   case viewport == drawing rectangle: no effects; break;
   case viewport < drawing rectangle:
      Pixels (after the viewport transformation but before expensive
      rastersizing and shading operations) which are outside of the
      viewport are discarded.
}

I am unable to find a test case where this improves performance, but in
all my testing it doesn't hurt performance, and intuitively, it should
not ever hurt performance. It also permits us to use the guardband more
freely (see upcoming patch).

v2: Updating commit message.

v3: Commit message updates requested by Ken

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-10 17:13:36 -07:00
Ben Widawsky
109d420f42 i965/guardband: Improve comments for guardband clipping
While working in this part of the code I had a great deal of trouble
understanding what it was trying to do, and matching it with the spec.
(mostly due bad wording in the PRM). To help future people, I've cleaned
up the wording and provided some ascii art.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-10 17:13:36 -07:00
Kenneth Graunke
31f1cbc24d i965: Support the allow_glsl_extension_directive_midshader option.
This adds support for Marek's new driconf parameter, which avoids
totally white rendering in Unigine Valley (which attempts to enable
the GL_ARB_sample_shading extension in an illegal place).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75664
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-08-10 16:22:31 -07:00
Connor Abbott
b6df68ba56 i965/fs: set virtual_grf_count in assign_regs()
This lets us call dump_instructions() after register allocation without
failing an assertion.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <connor.abbott@intel.com>
2014-08-10 15:00:53 -07:00
Connor Abbott
58007aec41 i965/fs: don't read from uninitialized memory while assigning registers
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <connor.abbott@intel.com>
2014-08-10 15:00:52 -07:00
Matt Turner
59a26a0554 i965/fs: Fix bad whitespace. 2014-08-10 15:00:52 -07:00
Niels Ole Salscheider
3d5e247de6 gallium/radeon: Set gpu_address to 0 if r600_virtual_address is false
Without this patch I get the following during DMA transfers:
[drm:radeon_cs_ib_chunk] *ERROR* Invalid command stream !
radeon 0000:01:00.0: CP DMA dst buffer too small (21475829792 4096)

This is a fixup for e878e154cd.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-08-10 12:54:34 +02:00
Marek Olšák
a65611f70a radeonsi: simplify constant buffer upload for big endian
Point util_memcpy_cpu_to_le32 to a buffer storage directly.

v2: simplify more

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-10 12:52:13 +02:00
Marek Olšák
b1843a2d2a winsys/radeon: fix compile warnings 2014-08-09 23:48:41 +02:00
Marek Olšák
b5f877ef7e r600g/compute: fix compile warnings
Trivial.
2014-08-09 23:41:16 +02:00
Marek Olšák
3d06952d9e r300g: handle new shader caps
Trivial.
2014-08-09 23:41:16 +02:00
Marek Olšák
955505f6ff radeonsi: fix CMASK and HTILE allocation on Tahiti
Tahiti has 12 tile pipes, but P8 pipe config.

It looks like there is no way to get the pipe config except for reading
GB_TILE_MODE. The TILING_CONFIG ioctl doesn't return more than 8 pipes,
so we can't use that for Hawaii.

This fixes a regression caused by 9b046474c9
on Tahiti.

v2: add an assertion and print an error on failure

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-09 23:41:16 +02:00
Marek Olšák
00ddf7a016 gallium/radeon: remove r600_resource_va
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:16 +02:00
Marek Olšák
8c235465cd gallium/radeon: use gpu_address from r600_resource
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:16 +02:00
Marek Olšák
f6c392a270 r600g: use gpu_address from r600_resource
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
1c03a690bf radeonsi: use gpu_address from r600_resource
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
e878e154cd gallium/radeon: store VM address in r600_resource
This will help to get rid of the buffer_get_virtual_address calls.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
43b5c34cc3 r600g: remove useless r600_resource_va calls
R600-R700 don't support virtual memory.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
0e229b8c5a radeonsi: always prefer SWITCH_ON_EOP(0) on CIK
The code is rewritten to take known constraints into account, while always
using 0 by default.

This should improve performance for multi-SE parts in theory.

A debug option is also added for easier debugging. (If there are hangs,
use the option. If the hangs go away, you have found the problem.)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

v2: fix a typo, set max_se for evergreen GPUs according to the kernel driver
2014-08-09 23:41:15 +02:00
Marek Olšák
515269b3a7 radeonsi: fix a hang with instancing in Unigine Heaven/Valley on Hawaii
This isn't documented anywhere, but it's the only thing that works
for this case.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00
Marek Olšák
085a861545 radeon,r200: fix buffer validation after CS flush
This validates all bound buffers (CB, ZB, textures, DMA) at the beginning
of CS. This fixes "bo->space_accouned" assertion failures.

Tested by: Jochen Rollwagen <joro-2013@t-online.de>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-08-09 23:41:15 +02:00