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gallium/radeon: use gpu_address from r600_resource

Browse source 
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2014-08-06 22:29:27 +02:00
parent f6c392a270
commit 8c235465cd
3 changed files with 14 additions and 21 deletions
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14
src/gallium/drivers/radeon/r600_query.c
View file

@ -171,8 +171,7 @@ static void r600_emit_query_begin(struct r600_common_context *ctx, struct r600_q
}
/* emit begin query */
va = r600_resource_va(ctx->b.screen, (void*)query->buffer.buf);
va += query->buffer.results_end;
va = query->buffer.buf->gpu_address + query->buffer.results_end;
switch (query->type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
@ -233,7 +232,8 @@ static void r600_emit_query_end(struct r600_common_context *ctx, struct r600_que
ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw, FALSE);
}
va = r600_resource_va(ctx->b.screen, (void*)query->buffer.buf);
va = query->buffer.buf->gpu_address;
/* emit end query */
switch (query->type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
@ -329,7 +329,7 @@ static void r600_emit_query_predication(struct r600_common_context *ctx, struct
/* emit predicate packets for all data blocks */
for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
unsigned results_base = 0;
uint64_t va = r600_resource_va(ctx->b.screen, &qbuf->buf->b.b);
uint64_t va = qbuf->buf->gpu_address;
while (results_base < qbuf->results_end) {
radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
@ -826,7 +826,6 @@ void r600_query_init_backend_mask(struct r600_common_context *ctx)
uint32_t *results;
unsigned num_backends = ctx->screen->info.r600_num_backends;
unsigned i, mask = 0;
uint64_t va;
/* if backend_map query is supported by the kernel */
if (ctx->screen->info.r600_backend_map_valid) {
@ -861,7 +860,6 @@ void r600_query_init_backend_mask(struct r600_common_context *ctx)
PIPE_USAGE_STAGING, ctx->max_db*16);
if (!buffer)
goto err;
va = r600_resource_va(ctx->b.screen, (void*)buffer);
/* initialize buffer with zeroes */
results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE);
@ -872,8 +870,8 @@ void r600_query_init_backend_mask(struct r600_common_context *ctx)
/* emit EVENT_WRITE for ZPASS_DONE */
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1));
radeon_emit(cs, va);
radeon_emit(cs, va >> 32);
radeon_emit(cs, buffer->gpu_address);
radeon_emit(cs, buffer->gpu_address >> 32);
r600_emit_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE, RADEON_PRIO_MIN);

9
src/gallium/drivers/radeon/r600_streamout.c
View file

@ -212,8 +212,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
t[i]->b.buffer_size) >> 2); /* BUFFER_SIZE (in DW) */
radeon_emit(cs, stride_in_dw[i]); /* VTX_STRIDE (in DW) */
} else {
uint64_t va = r600_resource_va(rctx->b.screen,
(void*)t[i]->b.buffer);
uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address;
update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i);
@ -239,8 +238,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
}
if (rctx->streamout.append_bitmask & (1 << i)) {
uint64_t va = r600_resource_va(rctx->b.screen,
(void*)t[i]->buf_filled_size) +
uint64_t va = t[i]->buf_filled_size->gpu_address +
t[i]->buf_filled_size_offset;
/* Append. */
@ -286,8 +284,7 @@ void r600_emit_streamout_end(struct r600_common_context *rctx)
if (!t[i])
continue;
va = r600_resource_va(rctx->b.screen,
(void*)t[i]->buf_filled_size) + t[i]->buf_filled_size_offset;
va = t[i]->buf_filled_size->gpu_address + t[i]->buf_filled_size_offset;
radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
radeon_emit(cs, STRMOUT_SELECT_BUFFER(i) |
STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) |

12
src/gallium/drivers/radeon/r600_texture.c
View file

@ -473,8 +473,7 @@ static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen
}
/* update colorbuffer state bits */
rtex->cmask.base_address_reg =
r600_resource_va(&rscreen->b, &rtex->cmask_buffer->b.b) >> 8;
rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
if (rscreen->chip_class >= SI)
rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
@ -597,7 +596,6 @@ r600_texture_create_object(struct pipe_screen *screen,
struct r600_texture *rtex;
struct r600_resource *resource;
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
uint64_t va;
rtex = CALLOC_STRUCT(r600_texture);
if (rtex == NULL)
@ -666,13 +664,13 @@ r600_texture_create_object(struct pipe_screen *screen,
}
/* Initialize the CMASK base register value. */
va = r600_resource_va(&rscreen->b, &rtex->resource.b.b);
rtex->cmask.base_address_reg = (va + rtex->cmask.offset) >> 8;
rtex->cmask.base_address_reg =
(rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
if (rscreen->debug_flags & DBG_VM) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
r600_resource_va(screen, &rtex->resource.b.b),
r600_resource_va(screen, &rtex->resource.b.b) + rtex->resource.buf->size,
rtex->resource.gpu_address,
rtex->resource.gpu_address + rtex->resource.buf->size,
base->width0, base->height0, util_max_layer(base, 0)+1, base->last_level+1,
base->nr_samples ? base->nr_samples : 1, util_format_short_name(base->format));
}