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Author SHA1 Message Date
Connor Abbott
336839bcd8 tu: Don't leave tile store CS writeable 
A rebase problem meant that the hunk leaving the CS not writeable again
was dropped. This isn't what was intended and caused a crash in the CS
code.

Because tu6_emit_gmem_stores() is now called inside a condition, we have
to move the enable/disable outside of it because changing to a
read-write buffer inside of a condition isn't currently supported.

Fixes: ba9d0ba9a0 ("turnip: Emit tile stores at subpass end time.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35993>
 2025-07-09 02:49:43 +00:00
Simon Perretta
ad66ebb686 pvr: enable partial vertex input dmas
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:59 +00:00
Simon Perretta
043e05768a pco: add support for more pack/unpack ops 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:59 +00:00
Simon Perretta
2983d23e63 pvr: reorder device setup to create the compiler context earlier 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:59 +00:00
Simon Perretta
ba4628a094 pco: allow empty/nop vertex shaders 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:59 +00:00
Simon Perretta
f06e14cc6c pvr: setup vk pipeline cache 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:59 +00:00
Simon Perretta
a4500abc75 pvr: store device uuid and build sha 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:59 +00:00
Simon Perretta
0751eb576d pco: enable translation of vs sysvals 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:58 +00:00
Simon Perretta
410bba0463 pco: support flat interpolation varyings 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:58 +00:00
Simon Perretta
c386c2f9e8 pvr, pco: point size handling 
Clamp point size to limits.
Emit default point size if required but none is provided.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:57 +00:00
Simon Perretta
dc6ea99fde pco, pygen: add f{min,max} support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:57 +00:00
Simon Perretta
1cd2bb58fb pco: skip vector coalescing if ssa srcs are repeatedly referenced 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:57 +00:00
Simon Perretta
9d23d92afa pco: handle frag/point coords sysvals 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:56 +00:00
Simon Perretta
74d50d7720 pco: add support for load_ubo 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:56 +00:00
Simon Perretta
d17d97a867 pco: remove per-device specialization of SPIR-V/NIR options 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:55 +00:00
Simon Perretta
6ff964dd03 pvr, pco: initial descriptor rework 
Use more Vulkan runtime/common functions.
Properly use the descriptor pool.
Start to remove legacy/unused constructs from PDS generation.
Support for UBO descriptors.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:55 +00:00
Simon Perretta
38d581d842 pvr: drop pvr_lower_nir 
This pass can now remain in the compiler as Vulkan-specific data will be
abstracted into the compiler-driver interface.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:54 +00:00
Frank Binns
08222dc461 pvr: add missing refcounting for descriptor set layouts 
Do this by switching to vk_descriptor_set_layout and making use of the helper
functions. This also has the bonus of less code in the driver.

Fixes a segfault seen when running glmark2-es2-wayland.

Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Co-authored-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:54 +00:00
Simon Perretta
51a3372ff2 pvr: clarify image/sampler state word packing 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:53 +00:00
Simon Perretta
8b8e33106d pco: additional helper functions for address refs 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:53 +00:00
Simon Perretta
e7d50a6781 pco: add pco nir algebraic pass boilerplate and basic lowering/opts 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:53 +00:00
Simon Perretta
087d439a52 pco: run dce pass until no more progress is made 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:52 +00:00
Luigi Santivetti
6ad0b59cc8 Revert "pvr: Implement VK_EXT_memory_budget" 
This reverts commit 97efa57531.

Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:52 +00:00
Simon Perretta
a22ad99bdd pvr: set device features/props/extensions to Vulkan 1.0 minimums (unless implemented) 
The KHR_shader_expect_assume dEQP tests use dynamic rendering without
first checking that the driver supports 1.3 or the
KHR_dynamic_rendering extension

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:52 +00:00
Simon Perretta
ac2460bb3c pvr: commonize limits 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:51 +00:00
Simon Perretta
b13fe4e7a7 pco: commonise pass macro, use on opt subpasses 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:51 +00:00
Simon Perretta
765e9d837d pco, pygen: validate phases and io allocations for ops 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:50 +00:00
Simon Perretta
c201332fff pco, pygen: iterators for igrps and the instrs they contain 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:50 +00:00
Simon Perretta
04f3b3a5c9 pco, pygen: track valid phases and io allocations for ops 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:49 +00:00
Simon Perretta
05912bcb60 pco: initial legalize pass/validation to handle hw restrictions 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:49 +00:00
Simon Perretta
4402649b01 pco, pygen: track which hw srcs map to op srcs/dests 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:49 +00:00
Simon Perretta
4e171bcf89 pco, pygen: further abstract src/dest references 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:48 +00:00
Simon Perretta
d552d5b278 pco, pygen: add support for bitwise logical ops 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:48 +00:00
Simon Perretta
c2787d1d12 pco, pygen: add support for unpck and conversions 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:47 +00:00
Simon Perretta
8c379b0c3e pco, pygen: add support for dma ld and add64_32 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:47 +00:00
Simon Perretta
ff51ba7e43 pco, pygen: add support for tst, movc instructions and s{lt,ge,eq,ne} ops 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:47 +00:00
Simon Perretta
f1b63fe3f9 pco, pygen: add fdiv/frcp support 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:46 +00:00
Simon Perretta
7fb0223c93 pco, pygen: support enum mappings for instances of two bitsets 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:46 +00:00
Simon Perretta
88ac50cbb2 pco, pygen: amend translation of srcs/dests with no mods 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:45 +00:00
Simon Perretta
e9c7afc217 pco, pygen: rework isa gen to support multi-instruction groups 
- Split encode and group mappings to allow the former to be re-used.
- Add custom zero value mapping for bitset enums.
- Enable optional enum mapping for ref mods (previously just op mods).
- Commonize nop/nop.end.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:45 +00:00
Simon Perretta
11238774a4 pco: amend z/w usage code 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:45 +00:00
Simon Perretta
6ca0f828fa pco: amend source validation tracking 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:44 +00:00
Simon Perretta
18ef63e365 pco: drop shader binary finalizing 
Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Acked-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33998>
 2025-07-08 23:10:44 +00:00
Mel Henning
b9a9f6cd53 meson: Allow unnecessary_transmutes for bindgen 
Otherwise I get hundreds of "unnecessary transmute" warnings
on rustc 1.88.0

Cc: mesa-stable
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: @LingMan
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35874>
 2025-07-08 20:51:44 +00:00
Luigi Santivetti
0eb67508bd vulkan/util: add vk_realloc2
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
Details
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Signed-off-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Reviewed-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35998>
 2025-07-08 20:22:13 +00:00
Sviatoslav Peleshko
8d22eb960b brw/disasm: Fix Gfx11 3src-instructions dst register disassembly 
The conversion from bit value to register file type is already done
by the brw_eu_inst_3src_a1_dst_reg_file in the FFC macro now, so doing it
again produced incorrect results.

Fixes: e7179232 ("intel/brw: Move encoding of Gfx11 3-src inside the inst helpers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13141
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35960>
 2025-07-08 19:49:09 +00:00
Rob Clark
5b619cc4b0 freedreno: Advertise external_only if we can't render 
Don't claim we can render to formats unconditionally.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:45 +00:00
Rob Clark
29c342649d freedreno: Avoid unnecessarily aligning to gmem_align_w 
If we aren't going to be rendering to this resource, we don't need to
take gmem alignment into account.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:45 +00:00
Rob Clark
70fe77f61b freedreno/a6xx: Allow suboptimal sampling formats when requested 
We prefer PoT block sizes for various reasons, but if we are asked to
import 12/24/48b formats for sampling we can do so.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:45 +00:00
Rob Clark
63b33eb4d9 dri: Correct handle-usage flags 
If we can only import for sampling from, don't tell the driver that we
want to render to the handle.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35982>
 2025-07-08 19:05:43 +00:00