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brw/disasm: Fix Gfx11 3src-instructions dst register disassembly

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The conversion from bit value to register file type is already done
by the brw_eu_inst_3src_a1_dst_reg_file in the FFC macro now, so doing it
again produced incorrect results.

Fixes: e7179232 ("intel/brw: Move encoding of Gfx11 3-src inside the inst helpers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13141
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35960>
This commit is contained in:
Sviatoslav Peleshko 2025-07-06 23:58:29 +03:00 • committed by Marge Bot
parent 5b619cc4b0
commit 8d22eb960b
1 changed files with 1 additions and 3 deletions
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4
src/intel/compiler/brw_disasm.c
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@ -986,10 +986,8 @@ dest_3src(FILE *file, const struct intel_device_info *devinfo,
if (devinfo->ver < 10 && is_align1)
return 0;
if (devinfo->ver >= 12)
if (devinfo->ver >= 12 || is_align1)
reg_file = brw_eu_inst_3src_a1_dst_reg_file(devinfo, inst);
else if (is_align1 && brw_eu_inst_3src_a1_dst_reg_file(devinfo, inst))
reg_file = ARF;
else
reg_file = FIXED_GRF;