So all CommandBuffers in a given CommandPool can reuse BOs for their
memory pools.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11695>
This commit adds the actual implementations, allowing to diverge while
still sharing code that depends on pool functionality.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11695>
The Gallium and Vulkan drivers will soon use different memory pool
implementation, but some pieces in libpanfrost depend on pan_pool. Let's
split the implementation so we have common bits still available while
letting the drivers implement what really matters: the allocation logic.
All the generic pieces are prefixed pan_pool, and what will become the
gallium implementation is prefixed panfrost_pool. We'll then duplicate
the panfrost_pool bits in panvk and prefix it with panvk_pool, and
implementations will start diverging from there.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11695>
Pass a memory pool to pan_blit_ctx_init() instead of creating a new pool.
Useful for Vulkan since the descriptor pool is at the command buffer
level and is thus shared by all blit batches. Doing this will save us a
BO ownership transfer.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11695>
The transient_bo has already been added to the BO list, no need to call
panfrost_batch_add_bo() a second time on the same BO.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11695>
The code was using a prim assembler after the tess stage, however
tess prims aren't necessarily the output prim types, so just put
the prim ids into the vertices at tess stage, and skip prim assembly.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11000>
This ensures space for the extra outputs is calculated in the
tes vertex outputs.
dEQP-VK.pipeline.misc.primitive_id_from_tess
Fixes: dacf8f5f5c ("draw: hook up final bits of tessellation")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11000>
This fixes a possible problem if a non-indexed draw comes in first
in a new batch, then the batch might not emit the index buffer.
I'm unsure if we see this, I just spotted it trying to fix alacritty
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11705>
ifind_msb_rev was introduced in a5747f8ab3.
ifind_msb_rev guards against src0 being both 0 or -1 at the same time.
That is always true. This patch changes it to check for those values
individually.
Spotted from a compile warning.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: a5747f8ab3 (\"nir: add opcodes for *find_msb_rev and lowering\")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11630>
+ 9.31% drawover:gdrv0 iris_dri.so [.] iris_binder_reserve_3d
+ 2.36% drawover:gdrv0 iris_dri.so [.] iris_binder_reserve_3d
If the app never uses compute, then the compute bindings bit will always
be dirty causing these two paths never get shortcuts.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11699>
Add PCI IDs based in pci_ids/i965_pci_ids.h and move crocus before
iris in driver_map[].
This allows Xorg to load the crocus driver since iris would claim
the devices handled by crocus (because the i915 kernel driver is
used for all Intel devices) then fail during initialization.
Signed-off-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11694>
The intention here was to pass VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT to
select_memory_types() when requesting device local memory, or simply
pass 0 for the prime blit destination which should be in system memory.
Unfortunately, that meant we did (type.propertyFlags & 0) == 0 which
was vacuously true, causing us to not filter out device local types.
Fixes hybrid display of Vulkan apps on Intel TGL+DG1 systems.
Tested-by: Luis Felipe Strano Moraes <luis.strano@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11680>
Even with the wrap mode forced to REPEAT, we get undefined results in
CelShading when the Y channel is unwritten since the beginning of the
program.
I dropped the coords==0 case in the process, since that's not possible and
made the 1D case confusing.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11457>
As written this would require that the driver be built before we looked
at the option. This is wrong because it affects code outside of the
driver, it's in libGL's PCI ID table. This is sort of harmless for
crocus at the moment, but for iris you would need to build it in order
to remove it from the table; if you built just i965 and tried to run it
against gen9, the libGL you just built would direct the loader to the
iris driver you just didn't, and setup would fail, which is: goofy.
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11655>
This was used in the heuristics for deciding whether to CPU map,
but those have since been deleted, so this is now unused.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11644>
If the caller has asked for a coherent BO with snooping, and the kernel
fails to set it for whatever reason, we were happily returning them a
non-coherent buffer. This isn't what they wanted and could lead to
surprising results.
Better to simply fail the allocation. Probably.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11644>
On integrated GPUs without LLC, we enable snooping when someone requests
coherency for a buffer. (With LLC, it's already coherent.)
For discrete GPUs...if someone requests coherency, we allocate the
buffer in SMEM and resort to WC maps rather than WB maps with CPU
caches enabled. There's no snooping to enable, and calling this ioctl
is nonsensical, and may fail.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11644>
With HTILE only, all values between 0.0 and 1.0 are fetchable.
This should allow more fast clears for depth surfaces where
TC-compat HTILE is disabled.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10035>
VK_EXT_depth_range_unrestricted removes the restriction that the
clear value must be between 0.0 and 1.0.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10035>
The HTILE clear code is now computed based on the floating point value.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10035>
For images, variable data includes the format. For samplers, variable
data is used for OpenCL inline samplers. When converting a variable
from one to the other, zero out the data so we don't accidentally
interpret a converted image as an inline sampler.
Fixes: fa677c86 ("nir_lower_readonly_images_to_tex: Support non-CL semantics")
Acked-by: Enrico Galli <enrico.galli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11674>
