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nir/ifind_msb_rev: fix input check

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ifind_msb_rev was introduced in a5747f8ab3.

ifind_msb_rev guards against src0 being both 0 or -1 at the same time.
That is always true. This patch changes it to check for those values
individually.

Spotted from a compile warning.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

Fixes: a5747f8ab3 (\"nir: add opcodes for *find_msb_rev and lowering\")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11630>
This commit is contained in:
Thomas H.P. Andersen 2021-06-29 00:54:40 +02:00 • committed by Marge Bot
parent 4504fabed6
commit ffea622604
1 changed files with 1 additions and 1 deletions
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2
src/compiler/nir/nir_opcodes.py
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@ -489,7 +489,7 @@ for (int bit = 31; bit >= 0; bit--) {
unop_convert("ifind_msb_rev", tint32, tuint, """
dst = -1;
if (src0 != 0 || src0 != -1) {
if (src0 != 0 && src0 != -1) {
for (int bit = 0; bit < 31; bit++) {
/* If src0 < 0, we're looking for the first 0 bit.
* if src0 >= 0, we're looking for the first 1 bit.