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radv: allow more fast clears for depth surfaces without TC-compat HTILE

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With HTILE only, all values between 0.0 and 1.0 are fetchable.
This should allow more fast clears for depth surfaces where
TC-compat HTILE is disabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10035>
This commit is contained in:
Samuel Pitoiset 2021-04-05 14:19:42 +02:00
parent 269795c838
commit e58ab64223
1 changed files with 4 additions and 3 deletions
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7
src/amd/vulkan/radv_meta_clear.c
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@ -980,9 +980,10 @@ radv_can_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, const struct radv_
(clear_value.depth < 0.0 || clear_value.depth > 1.0))
return false;
if (((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && !radv_is_fast_clear_depth_allowed(clear_value)) ||
((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
!radv_is_fast_clear_stencil_allowed(clear_value)))
if (radv_image_is_tc_compat_htile(iview->image) &&
(((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && !radv_is_fast_clear_depth_allowed(clear_value)) ||
((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
!radv_is_fast_clear_stencil_allowed(clear_value))))
return false;
return true;