Commit graph

135964 commits

Author SHA1 Message Date
Marek Olšák
3166d4428d radeonsi: set EXTRA_DX_DY_PRECISION for lines where it's supported
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700>
2021-11-16 02:11:46 +00:00
Marek Olšák
4571778008 radeonsi: set PERPENDICULAR_ENDCAP_ENA for wide AA lines
This is more correct.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700>
2021-11-16 02:11:45 +00:00
Marek Olšák
3338956268 radeonsi: make si_get_small_prim_cull_info static
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700>
2021-11-16 02:11:45 +00:00
Marek Olšák
963b7475a9 radeonsi: use ac_build_load_to_sgpr in gfx10_emit_ngg_culling_epilogue
This is more correct because we are loading constants into an SGPR even
though there is no effect on behavior in this case.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700>
2021-11-16 02:11:45 +00:00
Marek Olšák
f8a0aa6852 radeonsi: fix view culling for wide lines
We need to cull wide lines as quads, but only for view culling.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700>
2021-11-16 02:11:45 +00:00
Marek Olšák
8f687bb5dc radeonsi: fix shader culling with integer pixel centers
Only Nine was using them.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13700>
2021-11-16 02:11:45 +00:00
Ilia Mirkin
185826a400 nir: remove double-validation of src component counts
The nir_tex_instr_src_size helper already sorts this out correctly, no
need to do it twice, and validate_src takes care of it.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13781>
2021-11-16 01:23:41 +00:00
Bas Nieuwenhuizen
6e3266709a radv: Add more checking of cache sizes.
Hopefully prevents things.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13789>
2021-11-16 00:58:08 +00:00
Bas Nieuwenhuizen
9494c566c2 radv: Fix memory corruption loading RT pipeline cache entries.
Oops. Forgot to account for the size here.

Fixes: ca2d96db51 ("radv: Add caching for RT pipelines.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13789>
2021-11-16 00:58:08 +00:00
Ilia Mirkin
8c9a86cb57 freedreno/ir3: fix image-to-tex flags, remove 3d -> array hack
The function would return both the 3d and array flags set for 2d array,
and would return just 3d for cubes. Fix the flags so that they are
appropriate for images.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13804>
2021-11-16 00:33:31 +00:00
Paulo Zanoni
a9c1cc63c6 iris: call brw_process_intel_debug_variable() earlier
We're currently only calling it after creating the screen and the
bufmgr. There are a few cases where Iris checks for the DEBUG_BUFMGR
bit before we call brw_process_intel_debug_variable(), which means
intel_debug is 0 and so we don't run the debug code. Today, these are
all related to the creation of the workaround bo and its mmap.

I found this in a custom branch after I converted to INTEL_DEBUG an
environment variable that I had.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13780>
2021-11-15 23:33:18 +00:00
Vasily Khoruzhick
15013958d0 lima: enable PIPE_CAP_PREFER_POT_ALIGNED_VARYINGS
Mali4x0 PP doesn't have a swizzle for load_input, so use POT-aligned
varyings to avoid unnecessary movs for vec3 and precision downgrade
in case if this vec3 is coordinates for a sampler

shader-db:

total instructions in shared programs: 15707 -> 15623 (-0.53%)
instructions in affected programs: 3906 -> 3822 (-2.15%)
helped: 47
HURT: 18
helped stats (abs) min: 1 max: 9 x̄: 3.09 x̃: 2
helped stats (rel) min: 1.49% max: 23.53% x̄: 8.20% x̃: 6.45%
HURT stats (abs)   min: 1 max: 7 x̄: 3.39 x̃: 3
HURT stats (rel)   min: 0.78% max: 20.59% x̄: 10.45% x̃: 10.97%
95% mean confidence interval for instructions value: -2.18 -0.41
95% mean confidence interval for instructions %-change: -5.70% -0.38%
Instructions are helped.

total spills in shared programs: 146 -> 136 (-6.85%)
spills in affected programs: 39 -> 29 (-25.64%)
helped: 6
HURT: 0

total fills in shared programs: 617 -> 598 (-3.08%)
fills in affected programs: 125 -> 106 (-15.20%)
helped: 6
HURT: 0

HURT shaders are vertex shaders where we may need more instructions
for non-packed vec3s. It's acceptable trade-off since we don't get
precision downgrade if this varying is coordinates for a sampler.

Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13151>
2021-11-15 22:52:55 +00:00
Vasily Khoruzhick
3bb192a15b gallium: add PIPE_CAP_PREFER_POT_ALIGNED_VARYINGS
Driver should enable this cap if it prefers varyings to be aligned
to power of two in a slot, i.e. vec4 in .xyzw, vec3 in .xyz, vec2 in .xy
or .zw

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13151>
2021-11-15 22:52:55 +00:00
Emma Anholt
42753be1e7 freedreno/a6xx: Fix a bunch of 3D texture layout to match blob behavior.
This doesn't get all of the texelfetch sampler3d testcases working, but
it's sure a lot more.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13733>
2021-11-15 22:25:08 +00:00
Emma Anholt
a3717c1496 freedreno/cffdump: Handle the TILE_ALL flag in unit test generation.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13733>
2021-11-15 22:25:08 +00:00
Emma Anholt
e42450a255 freedreno/cffdump: Fix up formatting of texturator unit test script output.
Now I don't need to re-clang-format as I generate testcases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13733>
2021-11-15 22:25:08 +00:00
Emma Anholt
7a6fc25daa freedreno/fdl: Add support for unit testing 3D texture array strides.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13733>
2021-11-15 22:25:08 +00:00
Emma Anholt
0d7c6eedc7 freedreno/cffdump: Fix 64-bit reg decode in script mode.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13733>
2021-11-15 22:25:08 +00:00
Emma Anholt
f63fd3425d freedreno: Fix the texturator unit test script.
We no longer have reg defs for the HI fields, so all we can access from
lua is the low 32 bits.  LUA has only double-precision floats for numbers,
so we can't fix that.  However, the high bits are almost always the same,
so it's not that big of a deal to be ignoring them for this script.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13733>
2021-11-15 22:25:08 +00:00
Emma Anholt
3ddefb4ae3 freedreno/fdl: Dump the generated layout when a layout test fails.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13733>
2021-11-15 22:25:08 +00:00
Dave Airlie
4b27ebee7f util/vl: move gallium vl_vlc.h and vl_rbsp.h to shared code.
For vulkan video I need these to parse slice headers, so move
them somewhere easier to get at them.

drops pointer_to_uintptr in favour of a cast.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13768>
2021-11-15 21:57:28 +00:00
Jordan Justen
29c2f32a57 intel/dev: Add platform enum with DG2 G10 & G11
Based on Lionel's "intel/devinfo: store the different kind of DG2".

Ref: 361b3fee3c ("intel: move away from booleans to identify platforms")
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9e22cfc5e9b92556a56d8a564cdab31045f29010
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13797>
2021-11-15 21:39:27 +00:00
Mike Blumenkrantz
43c457a6ec zink: always add VK_IMAGE_CREATE_2D_ARRAY_COMPATIBLE_BIT for 3D images
there's no way to know what an image will be used for, so this bit needs
to always be added

fixes KHR-GL46.packed_pixels.varied_rectangle.compressed_rgb

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13798>
2021-11-15 21:24:05 +00:00
Mike Blumenkrantz
93a55537f2 zink: stop running discard_if in generated tcs
just embarrassing smh

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13798>
2021-11-15 21:24:05 +00:00
Samuel Pitoiset
df526aae1b zink: skip one GLES31 subset to avoid GPU hangs on Navi10
Weird bug... I will figure out later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13796>
2021-11-15 20:33:22 +00:00
Dave Airlie
bf7b6dd73f intel/genxml: generate video headers
This just generates the video engine pieces.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
8f9006804a intel/genxml: fix gen6 LD->VLD typo.
Pointed out by Ilia

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Matt Turner
2bb8aa2942 intel/genxml: capitalize decoder mode select properly
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
2268fc1bb6 intel/genxml: fix Picure->Picture typo
Ilia pointed this out.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
dc32a164c8 intel/genxml: align QM field names across gens.
This just picks a consistent name.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
0f3f8b4591 intel/genxml: fix some missing address from the 75 xml
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
5d956d65b6 intel/genxml: cleanup video xml collisions.
When you enable video genxml, lots of warnings about redefined things
appear, just clean those up before things get started.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Rhys Perry
d89461208b aco: consider pseudo-instructions reading exec in needs_exec_mask()
No matter the format, this should return true if the instruction has an
exec operand.

Otherwise, eliminate_useless_exec_writes_in_block() could remove an exec
write in a block if it's successor begins with:
 s2: %3737:s[8-9] = p_parallelcopy %0:exec
 s2: %0:exec,  s1: %3738:scc = s_wqm_b64 %3737:s[8-9]

Totals from 3 (0.00% of 150170) affected shaders (GFX10.3):
CodeSize: 23184 -> 23204 (+0.09%)
Instrs: 4143 -> 4148 (+0.12%)
Latency: 98379 -> 98382 (+0.00%)
Copies: 172 -> 175 (+1.74%)
Branches: 95 -> 97 (+2.11%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: bc13049747 ("aco: Eliminate useless exec writes in jump threading.")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5620
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13776>
2021-11-15 18:58:37 +00:00
Daniel Schürmann
7876886bdc radv: use nir_fold_16bit_sampler_conversions()
for now only for texture dest and if there is no rounding mode required.

Totals from 2 (0.00% of 150170) affected shaders: (GFX10.3)
CodeSize: 7980 -> 7948 (-0.40%)
Instrs: 1441 -> 1422 (-1.32%)
Latency: 7703 -> 7626 (-1.00%)
InvThroughput: 2336 -> 2302 (-1.46%)
VClause: 34 -> 36 (+5.88%)
Copies: 57 -> 58 (+1.75%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13592>
2021-11-15 18:28:20 +00:00
Daniel Schürmann
ab21183b5d aco: implement D16 texture loads
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13592>
2021-11-15 18:28:20 +00:00
Daniel Schürmann
626aa7b648 aco: workaround GFX9 hardware bug for D16 image instructions
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13592>
2021-11-15 18:28:20 +00:00
Daniel Schürmann
8f1483cd5c aco: add more D16 load/store instructions to RA and validator
This enables correct handling for
buffer_load/store_format_d16_x and
D16 Image instructions.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13592>
2021-11-15 18:28:20 +00:00
Daniel Schürmann
1e4c6e059e nir/fold_16bit_sampler_conversions: skip sparse residency tex instructions
The residency return value mismatches between NIR and Radeon.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13592>
2021-11-15 18:28:20 +00:00
Rob Clark
f53e1823c2 freedreno: caps for clover
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12500>
2021-11-15 18:06:39 +00:00
Rob Clark
9e7f5b75ec freedreno: Add PIPE_SHADER_IR_NIR_SERIALIZED support
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12500>
2021-11-15 18:06:39 +00:00
Ilia Mirkin
31d6cd224a a5xx: remove astc srgb workaround logic
This was copied from a4xx, which only needs it on one chip model (A420).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13782>
2021-11-15 17:31:53 +00:00
Samuel Pitoiset
cb56b83572 zink: update the CI lists for RADV
Lot of GPU hangs fixed lately.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13792>
2021-11-15 16:19:29 +00:00
Jesse Natalie
f0e5bc228c microsoft/clc: Add a test for arg metadata
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13759>
2021-11-15 07:47:06 -08:00
Jesse Natalie
53d4dc7feb clc: Use kernel_arg_type_qual string to add const type qualifier to arg metadata
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13759>
2021-11-15 07:47:00 -08:00
Iago Toral Quiroga
f384c763fc v3d,v3dv: move tile size calculation to a common helper
We had this code replicated in 3 places across both drivers.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13790>
2021-11-15 11:40:39 +00:00
Samuel Pitoiset
a9c4e0c371 ac/spm: fix determining the counter slot
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: e928f475cc ("ac: add initial SPM support")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13758>
2021-11-15 11:24:36 +01:00
Samuel Pitoiset
11c6a32759 ac/spm: fix determing the SPM wire
One SPM wire holds two 16-bit counters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: e928f475cc ("ac: add initial SPM support")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13758>
2021-11-15 11:24:33 +01:00
Samuel Pitoiset
e94a899c0e radv: fix a sync issue on GFX9+ by clearing the upload BO fence
If the same cmdbuf is submitted more than once, they were waiting on
the same fence value. Fix this by clearing the value when beginning
a new command buffer.

This might fix spurious GPU hangs, especially on GFX9.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5401
Cc: 21.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13777>
2021-11-15 09:59:53 +01:00
Timothy Arceri
9d9de15a02 mesa: fix buffer overrun in SavedObj texture obj array
Fixes: 3be42f9ca1 ("mesa: rewrite glPushAttrib/glPopAttrib to get rid of malloc")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5621

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13773>
2021-11-15 00:09:57 +00:00
Dave Airlie
27903abbb6 llvmpipe: fix compressed image sizes.
VK CTS just added some new tests to write to a compressed image
from a compute shader, which was overrunning memory.

The image width/height need to be sized according to the block
sizes to avoid overwriting memory.

dEQP-VK.image.sample_texture.*bit_compressed*

Cc: mesa-stable

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13618>
2021-11-15 07:15:36 +10:00