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radv: Fix memory corruption loading RT pipeline cache entries.

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Fixes: ca2d96db51 ("radv: Add caching for RT pipelines.")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13789>
This commit is contained in:
Bas Nieuwenhuizen 2021-11-14 23:57:45 +01:00 • committed by Marge Bot
parent 8c9a86cb57
commit 9494c566c2
1 changed files with 1 additions and 0 deletions
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src/amd/vulkan/radv_pipeline_cache.c
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@ -109,6 +109,7 @@ entry_size(struct cache_entry *entry)
for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; ++i)
if (entry->binary_sizes[i])
ret += entry->binary_sizes[i];
ret += sizeof(struct radv_pipeline_shader_stack_size) * entry->num_stack_sizes;
ret = align(ret, alignof(struct cache_entry));
return ret;
}