Commit graph

7322 commits

Author SHA1 Message Date
Sagar Ghuge
2fa68cb7da intel/fs: Define and set correct sampler simd mode
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Topi Pohjolainen
31e3e32625 intel/compiler: Deprecate ld2dms and use ld2dms_w instead
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Topi Pohjolainen
261dd6c8f8 intel/compiler: Add new variant for TXF_CMS_W
This allows, for example, fs_inst::components_read() without passing
devinfo as extra argument.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Topi Pohjolainen
24831bbd40 intel/compiler: Prepare ld2dms_w for 4 mcs components
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Topi Pohjolainen
dfe0ba9080 intel/compiler: Demote sampler params to 16-bit for CMS/UMS/MCS
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Topi Pohjolainen
0374b56faa intel/compiler/fs: Add support for 16-bit sampler msg payload
For SIMD8 half float payload, each component takes a full register, so
we can use existing LOAD_PAYLOAD infrastruture for required padding by
alternating plain 8-wide half float vector and null vector.

Also this patch removes an unwanted assertion from
opt_copy_propagation_local for LOAD_PAYLOAD.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Sagar Ghuge
936412af27 intel/compiler: Add helper to support half float payload with padding
To support SIMD8 half float payloads, each component takes one full
32bit wide register in both SIMD8H and SIMD16H mode. So we can make use
of existing LOAD_PAYLOAD infrastructure alternating a half float vector
and a null vector, in order to handle required padding.

v2: (Francisco)
- Skip header sources
- Fix comparision units
- Don't allocate VGRF for padded source

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggested-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Sagar Ghuge
75c73fcdc4 intel/compiler: Fix instruction size written calculation
We are always aligning to REG_SIZE but when we have payload sources less
than REG_SIZE, size written is miscalculated.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Sagar Ghuge
be2bfe5fe8 intel/compiler: Don't hardcode padding source type to 32bit
We can use LOAD_PAYLOAD infrastructure in order to handle 16bit float
payload. Let's rely on source type for padding sources, if not set
previously then default one would be 32-bit.

This patch will be used later in the series to handle 16-bit float
payloads.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Topi Pohjolainen
0e61d1fbbb intel/compiler: Handle new sampler descriptor fields for 16bit sampler
Update return format field and add SIMD Mode [2] field in sampler
descriptor. Now we can tell sampler to return data in either 32/16 bit
format precision.

v1:
- Drop unnecessary descriptor fields (Jason)
- Handle return format (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Sagar Ghuge
f78e33aa1a intel/compiler: Set correct return format for brw_SAMPLE
on GFX8 onwards, we have only single bit to determine correct return
format.

v2:
- Define macro and use it instead of hardcoded value. (Lionel)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
2021-11-22 21:27:30 -08:00
Lionel Landwerlin
5a2cff9bc8 intel: move timestamp scaling helper to intel/perf
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
2021-11-22 11:52:46 +00:00
Lionel Landwerlin
6126742648 intel/ds: remove verbose messages
At high frequency sampling, this generates a lot of messages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
2021-11-22 11:52:46 +00:00
Lionel Landwerlin
3d71e35857 intel/ds: isolate intel/perf from the pps-producer
Otherwise we need to include intel headers in generic code.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
2021-11-22 11:52:46 +00:00
Lionel Landwerlin
ed9116e545 intel/ds: drop unused constructors
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
2021-11-22 11:52:46 +00:00
Lionel Landwerlin
215dbfd131 intel/perf: track end timestamp of queries
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
2021-11-22 11:52:46 +00:00
Lionel Landwerlin
4ef6698a26 intel/ds: drop timestamp correlation code
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
2021-11-22 11:52:46 +00:00
Lionel Landwerlin
120f24cb36 intel/perf: add a helper to read timestamp from reports
On newer HW it will require more work than just reading a dword. It
could also vary depending on the report format.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
2021-11-22 11:52:46 +00:00
Lionel Landwerlin
8657fa6b86 pps: allow drivers to report timestamps in their own time domain
For this each driver must :

  - report its clock_id (if no particular clock just default to cpu
    boottime one)

  - be able to sample its clock (gpu_timestamp())

The PPSDataSource will then emit timestamp correlation events in the
trace ensuring perfetto is able to display GPU & CPU events
appropriately on its timeline.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13831>
2021-11-22 11:52:46 +00:00
Lionel Landwerlin
c5a42e4010 intel/fs: fix shader call lowering pass
Now that we removed the intel intrinsic and just use the generic one,
we can skip it in the intel call lowering pass and just deal with it
in the intel rt intrinsic lowering.

v2: rewrite with nir_shader_instructions_pass() (Jason)

v3: handle everything in switch (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 423c47de99 ("nir: drop the btd_resume_intel intrinsic")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12113>
2021-11-22 08:17:26 +00:00
Lionel Landwerlin
21ec880bf9 anv: initialize anv_bo_sync base fields
v2: zalloc

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: cbb13fae33 ("anv: Add a BO sync type")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13875>
2021-11-19 15:09:43 +00:00
Lionel Landwerlin
04bd5bb69b anv: don't try to close fd = -1
CID: 1464334

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13879>
2021-11-19 14:52:29 +00:00
Iván Briano
0388783a03 intel/nir: also allow unknown format for getting the size of a storage image
Fixes: fa251cf111 ("intel/nir: allow unknown format in lowering of storage images")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13847>
2021-11-17 21:06:23 +00:00
Jason Ekstrand
2a910071bc vulkan,anv: Auto-detect syncobj features
Instead of having a bunch of const vk_sync_type for each permutation of
vk_drm_syncobj capabilities, have a vk_drm_syncobj_get_type helper which
auto-detects features.  If a driver can't support a feature for some
reason (i915 got timeline support very late, for instance), they can
always mask off feature bits they don't want.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:54:27 -06:00
Jason Ekstrand
36b4d12f02 anv: Simplify submit_simple_batch()
BO waits aren't going away any time soon so using a syncobj here doesn't
really gain us anything.  It just makes it more complicated.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:54:27 -06:00
Jason Ekstrand
623e9ecd6d anv: Remove unnecessary syncobj wrappers
These are entirely unused except for the syncobj in submit_simple_batch.
We can use the libdrm wrappers for that as they're basically equivalent
and the core Vulkan sync code already depends on them.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:54:27 -06:00
Jason Ekstrand
36ea90a361 anv: Convert to the common sync and submit framework
This is, unfortunately, a large flag-day mega-commit.  However, any
other approach would likely be fragile and involve a lot more churn as
we try to plumb the new vk_fence and vk_semaphore primitives into ANV's
submit code before we delete it all.  Instead, we do it all in one go
and accept the consequences.

While this should be mostly functionally equivalent to the previous
code, there is one potential perf-affecting change.  The command buffer
chaining optimization no longer works across VkSubmitInfo structs.
Within a single VkSubmitInfo, we will attempt to chain all the command
buffers together but we no longer try to chain across a VkSubmitInfo
boundary.  Hopefully, this isn't a significant perf problem.  If it ever
is, we'll have to teach the core runtime code how to combine two or more
VkSubmitInfos into a single vk_queue_submit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:54:27 -06:00
Jason Ekstrand
87cf858946 anv: Use helpers in util/os_time.h in the query code
These are about to be the only use of anv_gettime_ns() so lets switch
them over so the next patch can delete the helper outright.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:54:27 -06:00
Jason Ekstrand
213edd1841 anv: Remove the last remnants of in/out fences
This should have been dropped as part of d44ea09e61 ("anv: Drop unused
sync_file and BO semaphore code") but we missed a few bits.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:54:27 -06:00
Jason Ekstrand
cbb13fae33 anv: Add a BO sync type
This is copy+paste from the BO implementation of anv_fence

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:54:27 -06:00
Jason Ekstrand
dc62695c3a anv: Delete ANV_SEMAPHORE_TYPE_DUMMY
It's never set as a semaphore type.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:54:27 -06:00
Jason Ekstrand
e3fda7ae78 vulkan/wsi/display: Wrap wsi_display_fence in a vk_sync
This gets rid of the bespoke vfunc interface in the WSI code.
Eventually, I'd love to get rid of wsi_display_fence entirely but
this at least makes it a lot more palatable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:54:27 -06:00
Jason Ekstrand
236ca76376 anv: Wire up the new status check
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:02:08 -06:00
Jason Ekstrand
955f329fbe anv: Use the new common device lost tracking
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13427>
2021-11-16 10:02:08 -06:00
Jason Ekstrand
e6b4678fdb anv: Move device memory maps back to anv_device_memory
This effectively partially reverts 13fe43714c ("anv: Add helpers in
anv_allocator for mapping BOs") where we both added helpers and reworked
memory mapping to stash the maps on the BO.  The problem comes with
external memory.  Due to GEM rules, if a memory object is exported and
then imported or imported twice,  we have to deduplicate the anv_bo
struct but, according to Vulkan rules, they are separate VkDeviceMemory
objects.  This means we either need to always map whole objects and
reference-count the map or we need to handle maps separately for
separate VkDeviceMemory objects.  For now, take the later path.

Fixes: 13fe43714c ("anv: Add helpers in anv_allocator for mapping BOs")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5612
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13795>
2021-11-16 15:18:03 +00:00
Kenneth Graunke
88e4d3809c intel/genxml: Decode VALIGN/HALIGN values in XY_BLOCK_COPY_BLT
For easier readability in INTEL_DEBUG=bat.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809>
2021-11-16 11:38:30 +00:00
Kenneth Graunke
406ff7473a intel/genxml: Fix XY_BLOCK_COPY_BLT destination tiling field type
Fixes: 2f58a63b2f ("intel/genxml: Add XY_BLOCK_COPY_BLT on Tigerlake and later.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809>
2021-11-16 11:38:30 +00:00
Kenneth Graunke
29025f66fd intel/genxml: Fix MI_FLUSH_DW to actually specify the length properly
Fixes: 569afd37f1 ("intel/genxml: Copy gen12.xml to gen125.xml")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809>
2021-11-16 11:38:30 +00:00
Kenneth Graunke
ebc0099d89 intel/genxml: Collapse leading underscores on prefixed value defines
We prefix names with an underscore to make them "safe" C identifiers
when necessary.  For example, a value of "32x32" would become "_32x32".

However, when specifying something like

   <field ... prefix="BLOCK_SIZE">
     <value name="32x32" value="0"/>
   </field>

we already have a prefix that makes the field name safe.  We'd rather
generate a name with a single underscore, i.e.

    #define BLOCK_SIZE_32x32 0

rather than

    #define BLOCK_SIZE__32x32 0

This also fixes up affected defines in crocus.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809>
2021-11-16 11:38:30 +00:00
Kenneth Graunke
cd7d3c7ae3 intel/genxml: Simplify prefix handling for field value lists
When a <field> tag has multiple <value> children, listing symbolic names
for possible field values, we generate #defines for each value, with an
optional prefix.  I don't know why, but this code was checking whether
self.default is None.  We want to generate the same list of #defines,
with a prefix, regardless of whether the field has a default value
specified or not.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13809>
2021-11-16 11:38:30 +00:00
Timur Kristóf
5aa39253cb nir: Rename nir_get_io_vertex_index_src and include per-primitive I/O.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13466>
2021-11-16 07:46:55 +00:00
Jordan Justen
29c2f32a57 intel/dev: Add platform enum with DG2 G10 & G11
Based on Lionel's "intel/devinfo: store the different kind of DG2".

Ref: 361b3fee3c ("intel: move away from booleans to identify platforms")
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9e22cfc5e9b92556a56d8a564cdab31045f29010
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13797>
2021-11-15 21:39:27 +00:00
Dave Airlie
bf7b6dd73f intel/genxml: generate video headers
This just generates the video engine pieces.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
8f9006804a intel/genxml: fix gen6 LD->VLD typo.
Pointed out by Ilia

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Matt Turner
2bb8aa2942 intel/genxml: capitalize decoder mode select properly
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
2268fc1bb6 intel/genxml: fix Picure->Picture typo
Ilia pointed this out.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
dc32a164c8 intel/genxml: align QM field names across gens.
This just picks a consistent name.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
0f3f8b4591 intel/genxml: fix some missing address from the 75 xml
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Dave Airlie
5d956d65b6 intel/genxml: cleanup video xml collisions.
When you enable video genxml, lots of warnings about redefined things
appear, just clean those up before things get started.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13788>
2021-11-15 20:13:46 +00:00
Lionel Landwerlin
d2ff2b9e4a anv: fix multiple wait/signal on same binary semaphore
We need to guarantee that when vkQueueSubmit() returns the application
can actually wait on a signaled semaphore/syncobj.

When using a thread to do the submission to i915, this gets a bit
tricky in the following case :

   A syncobj is used both as a wait & signal semaphore and has been
   signaled once already. It contains a fence before entering
   vkQueueSubmit().

   This means we need to reset the syncobj to ensure when we return
   from vkQueueSubmit(), the syncobj contains no stale fence.

   Currently in the Anv, the submission thread is in charge of putting
   the new fence in the syncobj and also picks up the wait fence
   directly from the syncobj. This means we can't reset the syncobj
   from vkQueueSubmit().

The solution to this has been pointed by Bas & Jason :

   In vkQueueSubmit(), clone the wait syncobj fence into a new
   temporary syncobj that will be destroy after submission and use
   this temporary syncobj as a wait fence for i915. This allows us to
   reset the original syncobj in vkQueueSubmit().

   For this to work with wait_before_signal behavior, we also need to
   do a wait-on-materialize on binary semaphores from vkQueueSubmit().
   Otherwise the application thread calling vkQueueSubmit() could race
   the submission thread and pick up the wrong fence when cloing.

v2: Use copy semantic for clone_syncobj_dma_fence() (Jason)
    Do the cloning prior to adding the syncobj to anv_queue_submit so
    that if the cloning fails don't have an invalid syncobj in
    anv_queue_submit (Jason)

v3: Fix another syncobj leak (Jason)

v4: Fix invalid argument order (Lionel)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4945
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11474>
2021-11-11 20:59:32 +00:00