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intel/fs: Define and set correct sampler simd mode

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Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>
This commit is contained in:
Sagar Ghuge 2020-07-13 18:32:14 -07:00
parent 31e3e32625
commit 2fa68cb7da
1 changed files with 3 additions and 0 deletions
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3
src/intel/compiler/brw_eu_defines.h
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@ -1354,6 +1354,9 @@ enum brw_message_target {
#define BRW_SAMPLER_SIMD_MODE_SIMD16 2
#define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3
#define GFX10_SAMPLER_SIMD_MODE_SIMD8H 5
#define GFX10_SAMPLER_SIMD_MODE_SIMD16H 6
/* GFX9 changes SIMD mode 0 to mean SIMD8D, but lets us get the SIMD4x2
* behavior by setting bit 22 of dword 2 in the message header. */
#define GFX9_SAMPLER_SIMD_MODE_SIMD8D 0