Sagar Ghuge f78e33aa1a intel/compiler: Set correct return format for brw_SAMPLE ... on GFX8 onwards, we have only single bit to determine correct return format. v2: - Define macro and use it instead of hardcoded value. (Lionel) Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Francisco Jerez <currojerez@riseup.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11766>		2021-11-22 21:27:30 -08:00
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blorp	anv,blorp,iris: Set MOCS for COMPUTE_WALKER post-sync operation	2021-11-08 23:29:51 +00:00
common	intel/dev: Add platform enum with DG2 G10 & G11	2021-11-15 21:39:27 +00:00
compiler	intel/compiler: Set correct return format for brw_SAMPLE	2021-11-22 21:27:30 -08:00
dev	intel/dev: Add platform enum with DG2 G10 & G11	2021-11-15 21:39:27 +00:00
ds	intel: move timestamp scaling helper to intel/perf	2021-11-22 11:52:46 +00:00
genxml	intel/genxml: Decode VALIGN/HALIGN values in XY_BLOCK_COPY_BLT	2021-11-16 11:38:30 +00:00
isl	intel/dev: Add platform enum with DG2 G10 & G11	2021-11-15 21:39:27 +00:00
nullhw-layer	intel/nullhw: fix build	2021-03-26 20:12:40 +00:00
perf	intel: move timestamp scaling helper to intel/perf	2021-11-22 11:52:46 +00:00
tools	intel: move away from booleans to identify platforms	2021-11-08 16:48:06 +00:00
vulkan	anv: initialize anv_bo_sync base fields	2021-11-19 15:09:43 +00:00
Makefile.perf.am	intel: Rename GEN_PERF prefix to INTEL_PERF in build files	2021-04-20 20:06:34 +00:00
meson.build	pps: Intel pps driver	2021-05-18 14:28:48 +00:00