Commit graph

27608 commits

Author SHA1 Message Date
Leo Liu
8d7ac0a4e4 vl/dri3: implement DRI3 BufferFromPixmap
We also need render to the front buffer of temporary X pixmap,
this is the case of when we using opengl as video out for vaapi.
the basic implementation is to pass pixmap ID to X server, and
then X will return dma-buf fd, we will get the buffer object
through this dma-buf fd.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu
858b329c2c vl/dri3: add support for resizing
When drawable size changed, PresentConfigureNotify event will be
emitted, by handling the event to re-allocate resized buffer.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu
96580ad593 vl/dri3: implement funciton for get dirty area
This will clear presentation area not covered by video content

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu
b0bd908284 vl/dri3: implement function for flush frontbuffer
Request drawable content in pixmap by calling DRI3 PresentPixmap,
and handle PresentIdleNotify event.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu
e1223282db vl/dri3: add back buffers support
This implements DRI3 PixmapFromBuffer. Create buffer objects, and
associate it to a dma-buf fd, and then pass this fd with a pixmap
ID to X server for creating pixmap object; also add a function
for wait events.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu
69ba9be4d2 vl/dri3: implement flushing for queued events
also place holder for present events handling

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu
758b1bbaa7 vl/dri3: register present events
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu
672e8d5e7e vl/dri3: set drawable geometry
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Leo Liu
12e5220e34 vl/dri3: add DRI3 support and implement create and destroy
Required functions into place for implementation, create screen
with device fd returned from X server, also bail out to DRI2
with certain conditions.

v2: -organize the error out path (Axel)
    -squash previous patch 1 and 2 into one (Emil)

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-05-16 16:28:51 -04:00
Jan Vesely
40c6d54e76 clover: grid_offset should be padded with 0 not 1
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-05-16 13:58:14 -04:00
Jan Vesely
9525f33164 clover: Handle PIPE_SHADER_IR_NIR in switch
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2016-05-15 20:05:10 -04:00
Rob Clark
277818ecfb freedreno/ir3: small standalone compiler cleanup
Don't hard-code the gpu-id anymore.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-15 17:25:48 -04:00
Rob Clark
f8840f471d freedreno/ir3: lower fdiv
Not sure how we didn't hit this already, but since we want fdiv
converted into mul + rcp, we should set this.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-15 17:25:48 -04:00
Rob Clark
53cde5e295 freedreno/ir3: handle VARYING_SLOT_PNTC
In the glsl->tgsi path, this already gets translated to VAR8, which
matches up with rasterizer->sprite_coord_enable.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-15 17:25:48 -04:00
Rob Clark
2f1581059b freedreno/ir3: disable TGSI specific hacks in nir case
When we got NIR directly from state tracker (vs using tgsi_to_nir) we
need to realize this and skip some TGSI specific hacks.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-15 17:25:48 -04:00
Rob Clark
784086f3c1 freedreno/ir3: add support for NIR as preferred IR
For now under debug flag, since only suitable for debugging/testing.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-15 17:25:47 -04:00
Ilia Mirkin
be2b13e3bf nv50/ir: avoid asserts when the state tracker feeds us bogus inputs
INTERP is defined (by me) to have to have a INPUT source. However the
state tracker does not always obey this. This happens due to varying
packing logic introducing additional mov's which can't always be undone.
Instead of just giving up, we instead try harder to find the original
input. This won't always be possible, for example with indirect
accesses. There's not much we can (easily) do about that though.

This fixes the remaining interpolateAt* failures in dEQP:

dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at*

some of which were asserting due to INTERP_* being passed a non-input.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-05-15 14:12:56 -04:00
Ilia Mirkin
9323d084ac nvc0: don't try to go through the push path for indirect draws
This fixes

dEQP-GLES31.functional.draw_indirect.draw_elements_indirect.*.default_attribute

These tests were causing a const vbo to be set up, and were small enough
draws that the logic was trying to go via the push path (which emits
data directly into the cmd stream rather than uploading a user vbo).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-05-15 10:48:39 -04:00
Ilia Mirkin
2ef3cdb07e nvc0/ir: make sure to align the second arg of TXD to 4, as we do for TEX
This was handled in handleTEX(), however the way the logic works, those
extra arguments aren't added on by then, so it did nothing. Instead we
must duplicate that bit here. GK110 appears to complain about
MISALIGNED_GPR, however it's reasonable to believe that GK104 has the
same requirements.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95403
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2016-05-15 10:48:39 -04:00
Tobias Klausmann
8c02939794 nv50,nvc0: add support for cull distances
Cull distances are just a special case of clip distances as far as the
hardware is concerned. Make sure that the relevant "planes" are enabled,
and flip the clip mode to cull for those.

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
[imirkin: add enables on nvc0, add nv50 support]
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
2016-05-15 10:48:39 -04:00
Tobias Klausmann
2be258ea18 gallium: Add a pipe cap for arb_cull_distance
This lets us safely enable or disable the extension as needed

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-05-14 08:28:17 +10:00
Nicolai Hähnle
a694c20ecf radeonsi/sid_tables: rename reg_table to sid_reg_table
This is purely cosmetic, making it easier to assign blame for space used
in the binary in case somebody else makes a similar cleanup effort in the
future.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-05-13 01:03:39 -05:00
Nicolai Hähnle
c7f73a70f0 radeonsi/sid_tables: store offset into global fields table instead of pointer
This avoids relocations in the final binary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-05-13 01:03:39 -05:00
Nicolai Hähnle
54ab39caaf radeonsi/sid_tables: store strings by offset instead of by pointer
This saves some space and avoids the need for relocations.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-05-13 01:03:39 -05:00
Nicolai Hähnle
ca8f71f4cb r600: remove TABLE_SIZE macro
Use ARRAY_SIZE instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-05-13 01:03:38 -05:00
Nicolai Hähnle
43ac091e4c r600: move alu_op_table to .c file
So that it gets compiled and emitted only once, saving space is the final
binary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-05-13 01:03:38 -05:00
Nicolai Hähnle
390c740b99 r600: move cf_op_table to .c file
So that it gets compiled and emitted only once, saving space is the final
binary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-05-13 01:03:38 -05:00
Nicolai Hähnle
a180e1d22d r600: move fetch_op_table to .c file
So that it gets compiled and emitted only once, saving space is the final
binary.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-05-13 01:03:37 -05:00
Nicolai Hähnle
6d350fb13f r600: protect r600_isa.h with extern "C"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-05-13 01:03:37 -05:00
Bas Nieuwenhuizen
ac77fb74a0 gallium/ddebug: Implement launch_grid.
Does not implement dumping info.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-13 07:43:46 +02:00
Bas Nieuwenhuizen
22b35122fa gallium/ddebug: Support compute states.
v2: Reuse the macro for bind & delete.

Note that may not be able to share the delete long-term as
pipe_compute_state contains members not in pipe_shader_state,
and we need to distinguish the pointer location if we add that
struct to the union.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-05-13 07:43:37 +02:00
Bas Nieuwenhuizen
5efe477b13 gallium/ddebug: Add passthrough for get_compute_param.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-13 07:39:12 +02:00
Leo Liu
bd9ae72459 vl/dri: fix close fd error out
fd should be set to -1 only if it got closed by pipe_loader_release.

Signed-off-by: Leo Liu <leo.liu@amd.com>
2016-05-12 18:26:48 -04:00
Samuel Pitoiset
988b09f9ac nvc0: fix indentation in nvc0_invalidate_resource_storage()
Trivial.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-12 21:37:08 +02:00
Samuel Pitoiset
abb3401095 nvc0: save some CPU cycles in nvc0_context_unreference_resources()
This reduces the number of loop iterations for invalidating buffers
and images.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-12 21:37:08 +02:00
Samuel Pitoiset
b8f0b00a9a nvc0: invalidate texture buffers for compute
This is a pretty rare situation but this can happen though.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-12 21:37:08 +02:00
Tim Rowley
2785f2f2d7 swr: properly expose compressed format support
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-12 14:12:18 -05:00
Ilia Mirkin
ba3f0b6d59 nvc0: fix gl_SampleMaskIn computation
The SAMPLEMASK semantic should only return the bits set covered by the
current invocation. However we were always retrieving the covmask, which
returns the covered samples of the whole pixel.

When not doing per-sample invocation, this is precisely what we want.
However when doing per-sample invocation, we have to select the
sampleid'th bit and only return that. Furthermore, this means that we
have to have a 1:1 correlation for invocations and samples.

This fixes most

dEQP-GLES31.functional.shaders.sample_variables.sample_mask_in.*

tests. A few failures remain due to disagreements about nr_samples==1
logic as well as what happens with MSAA x2 RTs when the shading fraction
is 0.5.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-11 20:39:27 -04:00
Ilia Mirkin
f5fe903002 nv50/ir: generalize interp fixups to be able to fixup anything
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-11 20:39:26 -04:00
Jason Ekstrand
1b72c31e1f nir/algebraic: Separate ffma lowering from fusing
The i965 driver has its own pass for fusing mul+add combinations that's
much smarter than what nir_opt_algebraic can do so we don't want to get the
nir_opt_algebraic one just because we didn't set lower_ffma.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-05-11 11:44:35 -07:00
Rob Clark
e1d80f8603 gallium: add NIR as a possible IR
Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-11 12:20:11 -04:00
Rob Clark
425dc4c4b3 gallium: refactor pipe_shader_state to support multiple IR's
The goal is to allow the pipe driver to request something other than
TGSI, but detect whether what is getting is TGSI vs what it requested.
The pipe drivers will always have to support TGSI (and convert that into
whatever it is that they prefer), but in some cases we should be able to
skip the TGSI intermediate step (such as glsl->nir vs glsl->tgsi->nir).

I think pipe_compute_state should get similar treatment.  Currently,
afaict, it has one user and one consumer, which has allowed it to be
sloppy wrt. supporting alternative IR's.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-11 12:20:11 -04:00
Rob Clark
4500d17245 freedreno: fix multi-layer transfer_map's
The use of transfer_inline_write() in TexSubImage path (see fb9fe352ea)
exposed a bug for "layer_first" resources (ie. a4xx) not setting correct
layer_stride.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-11 12:03:21 -04:00
Roland Scheidegger
430797843a gallivm: improve dumping of bitcode
Use GALLIVM_DEBUG=dumpbc for dumping of modules as bitcode.
Instead of a fixed llvmpipe.bc name, use ir_<modulename>.bc so multiple
modules can be dumped (albeit it might still overwrite previous modules,
particularly the modules from draw tend to always have the same name).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2016-05-11 04:43:35 +02:00
Vinson Lee
8d639138c7 swr: [rasterizer] Include cmath for std::isnan and std::isinf.
This patch fixes this build error.

  CXX      rasterizer/memory/libswrAVX_la-ClearTile.lo
In file included from rasterizer/memory/ClearTile.cpp:34:0:
./rasterizer/memory/Convert.h: In function ‘uint16_t Convert32To16Float(float)’:
./rasterizer/memory/Convert.h:170:9: error: ‘__builtin_isnan’ is not a member of ‘std’
     if (std::isnan(val))
         ^
./rasterizer/memory/Convert.h:170:9: note: suggested alternative:
<built-in>: note:   ‘__builtin_isnan’
./rasterizer/memory/Convert.h:176:14: error: ‘__builtin_isinf_sign’ is not a member of ‘std’
     else if (std::isinf(val))
              ^
./rasterizer/memory/Convert.h:176:14: note: suggested alternative:
<built-in>: note:   ‘__builtin_isinf_sign’

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95180
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-05-10 17:11:05 -07:00
Bas Nieuwenhuizen
3d21720d31 radeonsi: Set declared tessellation LDS size to hardware size.
The calculated limit gave problems on SI as it was > 32 KiB
and the hardware LDS size on SI is only 32 KiB. It isn't
correct anyway when processing multiple patches in a threadgroup.

As we potentially have any number of patches such that the
used LDS is at most the hardware LDS size, and exact size
per patch is not known at compile time, this seems like
the only valid bound.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-10 20:14:55 +02:00
Rob Clark
8623e599fc freedreno/ir3: size input/output arrays properly
We index into these based on var->data.driver_location, which might have
gaps (ie. two inputs, one w/ drvloc 0 and other 2).  This shows up in
(for example) 'bin/copyteximage 1D', but was only noticed recently due
to additional asserts.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-05-10 13:17:27 -04:00
Samuel Pitoiset
e46ac18ebe nvc0: enable compute support by default on GK110+
Compute support seems to be pretty stable now, and according to piglit
it doesn't seem to break 3D state.

As a side effect, this will expose ARB_compute_shader on GK110/GK208.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-05-10 17:47:01 +02:00
Marek Olšák
2b58bc4461 gallium/radeon: don't flush the GFX IB if DMA doesn't depend on it
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-05-10 17:20:09 +02:00
Marek Olšák
fb89f06698 radeonsi: consolidate radeon_add_to_buffer_list calls for DMA
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-05-10 17:20:09 +02:00