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nvc0/ir: make sure to align the second arg of TXD to 4, as we do for TEX

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This was handled in handleTEX(), however the way the logic works, those
extra arguments aren't added on by then, so it did nothing. Instead we
must duplicate that bit here. GK110 appears to complain about
MISALIGNED_GPR, however it's reasonable to believe that GK104 has the
same requirements.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95403
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
Ilia Mirkin 2016-05-14 19:25:15 -04:00
parent 8c02939794
commit 2ef3cdb07e
1 changed files with 14 additions and 0 deletions
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14
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
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@ -993,6 +993,20 @@ NVC0LoweringPass::handleTXD(TexInstruction *txd)
txd->dPdx[c].set(NULL);
txd->dPdy[c].set(NULL);
}
// In this case we have fewer than 4 "real" arguments, which means that
// handleTEX didn't apply any padding. However we have to make sure that
// the second "group" of arguments still gets padded up to 4.
if (chipset >= NVISA_GK104_CHIPSET) {
int s = arg + 2 * dim;
if (s >= 4 && s < 7) {
if (txd->srcExists(s)) // move potential predicate out of the way
txd->moveSources(s, 7 - s);
while (s < 7)
txd->setSrc(s++, bld.loadImm(NULL, 0));
}
}
return true;
}