Commit graph

27608 commits

Author SHA1 Message Date
Thomas Hellstrom
24ad7e16cd winsys/svga: Fix an uninitialized return value
Reported-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviwed-by: Brian Paul <brianp@vmware.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2016-03-04 13:54:38 +01:00
Oded Gabbay
914d4967d7 radeonsi: Do colorformat endian swap for PIPE_USAGE_STAGING
There is an old if statement (dated to 2011) that prevented doing
endian swap for colorformat, in case the buffer is marked as
PIPE_USAGE_STAGING.

This is now wrong because st_ReadPixels() reads into a destination
texture that is marked with PIPE_USAGE_STAGING. Therefore, even if
the texture is rendered correctly to the monitor, when reading it
back we get unswapped/wrong values.

This patch makes the check_rgba() function in gl-1.0-readpixsanity
piglit test pass in big-endian.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-03 09:20:08 +02:00
Oded Gabbay
ef5183faea r600g: Do colorformat endian swap for PIPE_USAGE_STAGING
There is an old if statement (dated to 2011) that prevented doing
endian swap for colorformat, in case the buffer is marked
as PIPE_USAGE_STAGING.

This is now wrong because st_ReadPixels() reads into a destination
texture that is marked with PIPE_USAGE_STAGING. Therefore, even if
the texture is rendered correctly to the monitor, when reading it
back we get unswapped/wrong values.

This patch makes the check_rgba() function in gl-1.0-readpixsanity
piglit test pass in big-endian.

v2: removed duplicate call to r600_colorformat_endian_swap() inside
evergreen_init_color_surface_rat()

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-03-03 09:20:08 +02:00
Tim Rowley
7bb193d28c mesa/build: add OpenSWR to build
Tested on Linux (centos, ubuntu, and suse variants)

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-02 18:38:42 -06:00
Tim Rowley
d003be2a30 gallium/docs - add OpenSWR documentation
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-02 18:38:41 -06:00
Tim Rowley
da4f95d168 gallium/target-helpers: add OpenSWR driver
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-02 18:38:41 -06:00
Tim Rowley
ea37602273 gallium/auxilary: more __cplusplus exports
swr driver which is written in C++ needs access to some more
gallium utility functions than are currently exposed.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-02 18:38:41 -06:00
Tim Rowley
c6e67f5a93 gallium/swr: add OpenSWR rasterizer
Acked-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-02 18:38:41 -06:00
Tim Rowley
2b2d3680bf gallium/swr: add OpenSWR driver
OpenSWR is a new software rasterizer for x86 processors designed
for high performance and high scalablility on visualization workloads.

Acked-by: Roland Scheidegger <sroland@vmware.com>
Acked-by: Jose Fonseca <jfonseca@vmware.com>
2016-03-02 18:38:41 -06:00
Samuel Pitoiset
b94a46aa8e gk110/ir: fix wrong emission of NOT modifier for VOTE
Spotted by Coverity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reported-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-03-02 20:36:18 +01:00
Thomas Hindoe Paaboel Andersen
535002f4da gallium/cso: fix indentation
Only one of these were recently introduced. However, since
we keep copy/pasting the same wrong indentation we should
probably just fix it.

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-03-02 08:55:20 -07:00
Marek Olšák
43f74ac67c gallium: fix PIPE_BIND_QUERY_BUFFER - PIPE_BIND_SCANOUT overlap
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-03-02 15:32:52 +01:00
Rob Clark
c4ae047cab freedreno/ir3: enable shareable shaders
Now that we are no longer using the pctx reference in the shader, drop
it and turn on shareable shaders.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-03-01 19:21:45 -05:00
Rob Clark
c3f2f8cbe4 freedreno/ir3: pass ctx to constant-emit code
Rather than fishing it out of the shader.  This removes the other big
user of shader->pctx.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-03-01 19:20:44 -05:00
Rob Clark
5fd152bae8 freedreno/ir3: add dev ptr to ir3_compiler
And use this for allocating bo's to hold the shader binary, rather than
accessing the dev via ctx ptr.  One step towards making shaders sharable
across contexts.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2016-03-01 19:20:33 -05:00
Dave Airlie
ac222626ad virgl: add support for passing render condition flags to host.
This just passes the extra blit info to fix the render condition
tests.

Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-03-01 15:50:00 +10:00
Marek Olšák
c54f38494c r600g: remove support for DRM < 2.12.0 2016-03-01 00:18:54 +01:00
Marek Olšák
b7da8fa11d r300g: remove support for DRM < 2.12.0 2016-03-01 00:18:54 +01:00
Marek Olšák
a5e2a173dd winsys/radeon: drop support for DRM 2.12.0 (kernel < 3.2)
in order to make some winsys interface changes easier

This distros should use new DRM if they want to use new Mesa:
  Distro    kernel  mesa    eol
  SLES 10   2.6.16  6.4.2   2016-07
  SLED 11   3.0     9.0.3   2022-03
  RHEL 5    2.6.18  6.5.1   2017-03
  RHEL 6    2.6.32  10.4.3  2020-11
  Debian 6  2.6.32  7.7.1   2016-02

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-03-01 00:18:54 +01:00
Marek Olšák
69a8e435ce radeonsi: also dump shaders on a VM fault
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-03-01 00:18:54 +01:00
Marek Olšák
18df72b50b radeonsi: dump full shader disassemblies into ddebug logs
including prolog and epilog disassemblies

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-03-01 00:18:54 +01:00
Marek Olšák
74b4ce81fb radeonsi: allow dumping shader disassemblies to a file
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-03-01 00:18:54 +01:00
Marek Olšák
d0f3b524cd radeonsi: use re-Z
This can increase perf for shaders that kill pixels (kill, alpha-test,
alpha-to-coverage).

v2: add comments

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-03-01 00:18:19 +01:00
Marek Olšák
09bfbd43a0 tgsi/scan: count memory instructions
for radeonsi

Reviewed-by: Brian Paul <brianp@vmware.com>
2016-03-01 00:11:32 +01:00
Axel Davy
83bc2acfe9 st/nine: Fix second Multithreading issue with MANAGED buffers
Here is another threading issue with MANAGED buffers:

Thread 1: buffer creation
Thread 1: buffer lock
Thread 2: Draw call
Thread 1: writes data
Thread 1: Unlock

Without this patch, the buffer is initially dirty
and in the list of things to upload after its creation.
The draw call will then upload the data and unset the dirty flag,
and the Unlock won't trigger a second upload.

Fixes regression introduced by cc0114f30b:
"st/nine: Implement Managed vertex/index buffers"

Cc: "11.2" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-02-29 18:55:58 +01:00
Axel Davy
44246fe99d st/nine: Fix Multithreading issue with MANAGED buffers
d3d calls are protected by mutexes, however if app is doing in
two threads:

Thread 1: buffer Lock
Thread 2: Draw call
Thread 1: writes data
Thread 1: Unlock

Then before this patch, the Draw call would begin to upload
the buffer.

Solves this by moving the moment we add the buffer to the queue
of things to upload (We move it from Lock time to Unlock time).

Cc: "11.2" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-02-29 18:55:58 +01:00
Axel Davy
35c858c42c st/nine: Handle READONLY for buffer MANAGED pool
READONLY won't trigger an upload.

Cc: "11.2" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-02-29 18:55:58 +01:00
Axel Davy
8a8affdfda st/nine: Use Position input helper for ps3 declared inputs
When the semantic is Position (which can happen with index 0 only),
use the helper to get Position input.

Cc: "11.2" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-02-29 18:55:58 +01:00
Axel Davy
f08c990af5 st/nine: Introduce helper for Position shader input
Cc: "11.2" <mesa-stable@lists.freedesktop.org>

Signed-off-by: Axel Davy <axel.davy@ens.fr>
2016-02-29 18:55:58 +01:00
Koop Mast
04bc09fdf9 st/clover: Add libelf cflags to the build
Otherwise the build will fail, when the library is in a non default
location.

v2 [Emil Velikov]
 - drop the unneeded cflags from targets/opencl.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Fixes: 7f585a6a98 "configure.ac: use pkg-config for libelf"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93524
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-02-29 11:30:15 +00:00
Rob Herring
51b22bd468 r600: Make enum alu_op_flags unsigned
In builds with clang, there are several errors related to the enum
alu_op_flags like this:

src/gallium/drivers/r600/sb/sb_expr.cpp:887:8:
error: case value evaluates to -1610612736, which cannot be narrowed to
type 'unsigned int' [-Wc++11-narrowing]

These are due to the MSB being set in the enum. Fix these errors by
making the enum values unsigned as needed. The flags field that stores
this enum also needs to be unsigned.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-02-29 10:51:45 +00:00
Rob Herring
92dd38df5a gallium/radeon: Add space between string literal and identifier
Fix compiles with clang that have this C++11 error:

src/gallium/drivers/radeon/r600_pipe_common.h:662:34:
error: invalid suffix on literal; C++11 requires a space between literal
and identifier [-Wreserved-user-defined-literal]

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Cc: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-02-29 10:51:45 +00:00
Rob Herring
0156a33aa3 freedreno: drop unnecessary -Wno-packed-bitfield-compat
Enabling this warning doesn't generate any warnings with gcc, but is an
unknown option for clang, so drop it.

Signed-off-by: Rob Herring <robh@kernel.org>
Acked-by: Rob Clark <robdclark@gmail.com> (v1)

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
v2: keep the warning around, commented out
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-02-29 10:51:45 +00:00
Rob Herring
8949edf018 Android: clean-up and fix DRI module path handling
MESA_DRI_MODULE_PATH is only getting set for classic DRI drivers and may or
may not be set correctly for gallium_dri.so depending on the makefile
include ordering. For Android 6 and earlier it is fine, but with build
system changes in AOSP master, it is not.

Move the path variables to a single place at the top level and introduce
MESA_DRI_MODULE_REL_PATH for Android 5 and later which require relative
paths. With this, there is a single variable to change.

Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-02-29 10:51:44 +00:00
Rob Herring
574a92b048 Android: fix build break from nir/glsl move to compiler/
Commits a39a8fbbaa ("nir: move to compiler/") and eb63640c1d
("glsl: move to compiler/") broke Android builds. Fix them.

There is also a missing dependency between generated NIR headers and
several libraries. This isn't a new issue, but seems to have been
exposed by the NIR move.

Built with i915, i965, freedreno, r300g, r600g, vc4, and virgl enabled.

Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Cc: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2016-02-29 10:51:44 +00:00
Oded Gabbay
a640ad15e1 gallium/radeon: disable evergreen_do_fast_color_clear for BE
This function is currently broken for BE. I assume it's because of
util_pack_color(). Until I fix this path, I prefer to disable it so users
would be able to see correct colors on their desktop and applications.

Together with the two following patches:
- gallium/r600: Don't let h/w do endian swap for colorformat
- gallium/radeon: remove separate BE path in r600_translate_colorswap

it fixes BZ#72877 and BZ#92039

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-29 12:26:27 +02:00
Oded Gabbay
e3dfc0e095 gallium/r600: Don't let h/w do endian swap for colorformat
Since the rework on gallium pipe formats, there is no more need to do
endian swap of the colorformat in the h/w, because the conversion between
mesa format and gallium (pipe) format takes endianess into account (see
the big #if in p_format.h).

v2: return ENDIAN_NONE only for four 8-bits components
(V_0280A0_COLOR_8_8_8_8)

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-29 12:26:27 +02:00
Oded Gabbay
9559071ed6 gallium/radeon: remove separate BE path in r600_translate_colorswap
After further testing, it appears there is no need for
separate BE path in r600_translate_colorswap()

The only fix remaining is the change of the last if statement, in the 4
channels case. Originally, it contained an invalid swizzle configuration
that never got hit, in LE or BE. So the fix is relevant for both systems.

This patch adds an additional 120 available visuals for LE and BE,
as seen in glxinfo

v2:
Tested for regressions by running piglit gpu.py with CAICOS (r600g) on
x86-64 machine. No regressions found.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-29 12:26:27 +02:00
Samuel Pitoiset
07ed003faf nv50/ir: emit VOTE instruction
Changes from v2:
 - add missing NOT modifier for GK110/GM107

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-28 23:58:11 +01:00
Samuel Pitoiset
b3efa0a59e gk110/ir: add ld lock/st unlock emission
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-28 19:20:20 +01:00
Ilia Mirkin
aa3b85fd18 nv50,nvc0: bump minimum texture buffer offset alignment
It appears that it actually needs to be aligned to the datum size, so it
was 1 when testing with R8, but it can be as high as 16 with RGBA32.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-02-27 16:26:34 -05:00
Samuel Pitoiset
aad48f8691 nvc0: rework nvc0_compute_validate_program()
Reduce the amount of duplicated code by re-using
nvc0_program_validate(). While we are at it, change the prototype
to return void and remove nvc0_compute.h which is now useless.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-26 14:00:27 +01:00
Samuel Pitoiset
e1f5c76047 nvc0: make sure to validate compute global buffers on Fermi
No reason to not validate those global buffers and this might avoid
fails if someone try to use the global memory from compute programs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-26 14:00:23 +01:00
Samuel Pitoiset
dcf7938833 nvc0: move nvc0_validate_global_residents() to nvc0_compute.c
While we are at it, rename it to nvc0_compute_validate_globals() and
update its prototype.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre Moreau <pierre.morrow@free.fr>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
2016-02-26 14:00:18 +01:00
Dave Airlie
840aa52f50 virgl: add missing CAP turned off. 2016-02-26 04:03:09 +00:00
Emil Velikov
b08dbc84fe st/nine: don't forget to bundle the nine_limits.h file
Without this mesa 11.2.0-rc1 ended up busted :-(

Cc: "11.2" <mesa-stable@lists.freedesktop.org>
Repored-by: Ondřej Súkup <mimi.vx@gmail.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
2016-02-25 19:56:07 +00:00
Oded Gabbay
439b5b008f gallium/radeon: return correct values for BE in r600_translate_colorswap
Because I changed the swizzle check, I also need to adapt the return
values for each check.

It's basically almost the same as before, we just cross between STD and
STD_REV, and cross between ALT and ALT_REV

This fixes the rgba test in gl-1.0-readpixsanity (piglit) and also
fixes tri-flat (mesa demos).

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-25 09:21:08 +02:00
Oded Gabbay
ff8b41b702 gallium: remove duplicate define from enum pipe_format
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-02-25 09:21:08 +02:00
Oded Gabbay
4b7e219e61 gallium/radeon: Correctly translate colorswaps for big endian
The current code in r600_translate_colorswap uses the swizzle information
to determine which colorswap to use.

This works for BE & LE when the nr_channels is <4, but when nr_channels==4
(e.g. PIPE_FORMAT_A8R8G8B8_UNORM), this method can not be used for both BE
and LE, because the swizzle info is the same for both of them.

As a result, r600g doesn't support 24bit color formats, only 16bit, which
forces the user to choose 16bit color in X server.

This patch fixes this bug by separating the checks for LE and BE and
adapting the swizzle conditions in the BE part of the checks.

Tested on an Evergreen GPU (Cedar GL FirePro 2270) running inside POWER7
Big-Endian Machine.

Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
CC: "11.2" "11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-02-23 20:55:40 +02:00
Marek Olšák
190a291b03 tgsi/scan: handle holes between VS inputs, assert-fail in other cases
"st/mesa: overhaul vertex setup for clearing, glDrawPixels, glBitmap"
added a vertex shader declaring IN[0] and IN[2], but not IN[1].

Drivers relying on tgsi_shader_info can't handle holes in declarations,
because tgsi_shader_info doesn't track that.

This is just a quick workaround meant for stable that will work for vertex
shaders.

This fixes radeonsi DrawPixels and CopyPixels crashes.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
2016-02-23 16:42:16 +01:00