fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-03-09 20:20:33 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

freedreno/ir3: enable shareable shaders

Browse source 
Now that we are no longer using the pctx reference in the shader, drop
it and turn on shareable shaders.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
This commit is contained in:
Rob Clark 2016-03-01 17:51:36 -05:00
parent c3f2f8cbe4
commit c4ae047cab
5 changed files with 12 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/gallium/drivers/freedreno/a3xx/fd3_program.c
View file

@ -51,7 +51,8 @@ create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state
enum shader_t type)
{
struct fd3_shader_stateobj *so = CALLOC_STRUCT(fd3_shader_stateobj);
so->shader = ir3_shader_create(pctx, cso, type);
struct ir3_compiler *compiler = fd_context(pctx)->screen->compiler;
so->shader = ir3_shader_create(compiler, cso, type);
return so;
}

3
src/gallium/drivers/freedreno/a4xx/fd4_program.c
View file

@ -51,7 +51,8 @@ create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state
enum shader_t type)
{
struct fd4_shader_stateobj *so = CALLOC_STRUCT(fd4_shader_stateobj);
so->shader = ir3_shader_create(pctx, cso, type);
struct ir3_compiler *compiler = fd_context(pctx)->screen->compiler;
so->shader = ir3_shader_create(compiler, cso, type);
return so;
}

6
src/gallium/drivers/freedreno/freedreno_screen.c
View file

@ -241,7 +241,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_DEPTH_BOUNDS_TEST:
case PIPE_CAP_TGSI_TXQS:
case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
case PIPE_CAP_SHAREABLE_SHADERS:
case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
case PIPE_CAP_CLEAR_TEXTURE:
case PIPE_CAP_DRAW_PARAMETERS:
@ -257,6 +256,11 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_MAX_VIEWPORTS:
return 1;
case PIPE_CAP_SHAREABLE_SHADERS:
if (is_ir3(screen))
return 1;
return 0;
/* Stream output. */
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
if (is_ir3(screen))

5
src/gallium/drivers/freedreno/ir3/ir3_shader.c
View file

@ -266,14 +266,13 @@ ir3_shader_destroy(struct ir3_shader *shader)
}
struct ir3_shader *
ir3_shader_create(struct pipe_context *pctx,
ir3_shader_create(struct ir3_compiler *compiler,
const struct pipe_shader_state *cso,
enum shader_t type)
{
struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
shader->compiler = fd_context(pctx)->screen->compiler;
shader->compiler = compiler;
shader->id = ++shader->compiler->shader_count;
shader->pctx = pctx;
shader->type = type;
if (fd_mesa_debug & FD_DBG_DISASM) {
DBG("dump tgsi: type=%d", shader->type);

3
src/gallium/drivers/freedreno/ir3/ir3_shader.h
View file

@ -241,7 +241,6 @@ struct ir3_shader {
struct ir3_compiler *compiler;
struct pipe_context *pctx; /* TODO replace w/ pipe_screen */
nir_shader *nir;
struct pipe_stream_output_info stream_output;
@ -250,7 +249,7 @@ struct ir3_shader {
void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
struct ir3_shader * ir3_shader_create(struct pipe_context *pctx,
struct ir3_shader * ir3_shader_create(struct ir3_compiler *compiler,
const struct pipe_shader_state *cso, enum shader_t type);
void ir3_shader_destroy(struct ir3_shader *shader);
struct ir3_shader_variant * ir3_shader_variant(struct ir3_shader *shader,