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Author SHA1 Message Date
Samuel Pitoiset
25e28819bd ac/perfcounter: adjust the number of events for TD on GFX10.3 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39013>
 2025-12-22 09:47:21 +01:00
Samuel Pitoiset
a4cb114f5a ac/perfcounter: add a separate group for GFX10.3 
This is just a copy&paste but GFX10.3 has way more counters than GFX10
that will be added later.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39013>
 2025-12-22 09:47:09 +01:00
Daniel Schürmann
1e8d367537 amd: add and use ac_cu_info::has_vtx_format_alpha_adjust_bug 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38701>
 2025-12-22 07:34:48 +00:00
Daniel Schürmann
febc29907c amd: add and use ac_cu_info::has_gfx6_mrt_export_bug 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38701>
 2025-12-22 07:34:47 +00:00
Daniel Schürmann
7b7bdb76ab amd: add ac_cu_info::has_point_sample_accel flag and use in ACO 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38701>
 2025-12-22 07:34:47 +00:00
Daniel Schürmann
cfb745592d amd: add ac_cu_info::has_mad32 flag and use in ACO 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38701>
 2025-12-22 07:34:47 +00:00
Daniel Schürmann
f7c4aa48a0 ac/gpu_info: add some more flags to ac_cu_info 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38701>
 2025-12-22 07:34:46 +00:00
Daniel Schürmann
6f4e8046b5 ac/gpu_info: create separate function ac_fill_cu_info() to fill out CU info 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38701>
 2025-12-22 07:34:45 +00:00
Daniel Schürmann
749c619c45 ac/gpu_info: correct some SGPR and VGPR allocation values in ac_cu_info 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38701>
 2025-12-22 07:34:45 +00:00
Daniel Schürmann
553b431aca ac/gpu_info: move some CU information into separate struct ac_cu_info 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38701>
 2025-12-22 07:34:44 +00:00
Daniel Schürmann
d94e90df25 amd/common: link with libamdgpu_addrlib 
ac_surface needs that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38701>
 2025-12-22 07:34:41 +00:00
Daniel Schürmann
f930ecdc55 amd: add newer small APUs to get_task_num_entries() 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38999>
 2025-12-19 13:03:49 +00:00
Pierre-Eric Pelloux-Prayer
645fff5dae ac/descriptors: account for num_storage_samples for gfx10
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This fixes a page fault when nr_samples=4 but nr_storage_samples=2.
Based on si_is_format_supported this is only supported for color
formats and when has_eqaa_surface_allocator is true (< GFX11).

The referenced commit below didn't introduce the issue but it
exposed it by forcing the gfx blit path to be used.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13255
Fixes: 3424e16ece ("radeonsi: add decision code to select when to use CB_RESOLVE for performance")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38925>
 2025-12-18 10:45:49 +00:00
Emma Anholt
059d301c79 nir: Drop the mode argument of nir_lower_vars_to_scratch(). 
It only makes sense for function temps, and that's the only way it's been
used.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37245>
 2025-12-17 19:50:28 +00:00
Samuel Pitoiset
f8feed17e1 ac,radv,radeonsi: add tracked register macros to common code 
Because the tracked registers are really driver dependant, the driver
is expected to handle the tracked_registers struct itself.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38740>
 2025-12-17 15:09:26 +00:00
Samuel Pitoiset
c580fc667f ac,radv: add ac_cmdbuf::context_roll and use it 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38740>
 2025-12-17 15:09:26 +00:00
Samuel Pitoiset
f3b385859a ac,radv: add more cmdbuf emit helpers 
Some can't be shared with RadeonSI because it uses templates in some
places.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38740>
 2025-12-17 15:09:25 +00:00
Samuel Pitoiset
262fc80e45 ac,radv,radeonsi: add functions to initialize tracked regs 
Also initialize the new slots for RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38740>
 2025-12-17 15:09:25 +00:00
Samuel Pitoiset
44314e1ea6 ac,radv,radeonsi: add ac_tracked_regs 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38740>
 2025-12-17 15:09:24 +00:00
Samuel Pitoiset
fad24d6fcc ac/cmdbuf: add new slots to ac_tracked_reg 
For RADV registers that aren't tracked in RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38740>
 2025-12-17 15:09:23 +00:00
Samuel Pitoiset
18bdb76408 ac,radeonsi: move si_tracked_reg to common code 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38740>
 2025-12-17 15:09:22 +00:00
Timur Kristóf
0324700c03 radv: Use zero-filled BO for GFX6 and GFX10 null index buffer bug 
GFX10 hangs when drawing from a 0-sized index buffer.
GFX6 has a HW bug when the index buffer	address is 0.

Looking at VK CTS runs, GFX6 still triggers VM faults despite the
current mitigation, and it also tries to access memory when the
index buffer is zero sized. So it looks like GFX6 and GFX10
really have the same bug.

Let's share the mitigation between the two.
Use a zero-filled BO instead of the upload buffer.
This fixes VM faults on GFX6, and should speed up GFX10 a bit.

Note that the zero-filled BO is also going to be used for
other bug mitigations on GFX6-7.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38958>
 2025-12-15 21:03:19 +00:00
Georg Lehmann
da197c3d55 ac/nir/lower_ps_late: remove gfx6 mrtz writemask workaround 
This is now done in the backends.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38853>
 2025-12-12 17:00:51 +00:00
Rhys Perry
b5cf3b1628 ac/nir: fix check for increasing size of non-descriptor loads
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In the previous version, "end" could have been zero, which would have
allowed an increase of "mul" bytes, when it should not not be increased at all.

For example:
- align_offset=4
- mul=4
- unaligned_new_size=96
- aligned_new_size=128
This would have loaded a dword which was not loaded previously.

fossil-db (gfx1201):
Totals from 115 (0.14% of 79839) affected shaders:
Instrs: 286697 -> 287097 (+0.14%); split: -0.16%, +0.30%
CodeSize: 1477728 -> 1481256 (+0.24%); split: -0.13%, +0.37%
SpillSGPRs: 1662 -> 1658 (-0.24%); split: -0.42%, +0.18%
Latency: 2288612 -> 2290248 (+0.07%); split: -0.04%, +0.11%
InvThroughput: 467307 -> 467602 (+0.06%); split: -0.03%, +0.10%
VClause: 3689 -> 3691 (+0.05%)
SClause: 5052 -> 5064 (+0.24%); split: -0.20%, +0.44%
Copies: 34837 -> 35103 (+0.76%); split: -0.80%, +1.56%
Branches: 7402 -> 7401 (-0.01%)
PreSGPRs: 9147 -> 9143 (-0.04%); split: -0.44%, +0.39%
VALU: 159333 -> 159372 (+0.02%); split: -0.01%, +0.04%
SALU: 52047 -> 52276 (+0.44%); split: -0.55%, +0.99%
SMEM: 9556 -> 9697 (+1.48%)

fossil-db (navi31):
Totals from 238 (0.30% of 79825) affected shaders:
Instrs: 484480 -> 485105 (+0.13%); split: -0.05%, +0.17%
CodeSize: 2514012 -> 2517928 (+0.16%); split: -0.06%, +0.22%
SpillSGPRs: 1064 -> 1059 (-0.47%)
Latency: 3941121 -> 3944670 (+0.09%); split: -0.04%, +0.13%
InvThroughput: 897483 -> 898090 (+0.07%); split: -0.04%, +0.11%
VClause: 7101 -> 7098 (-0.04%)
SClause: 9036 -> 9052 (+0.18%); split: -0.44%, +0.62%
Copies: 42790 -> 43096 (+0.72%); split: -0.30%, +1.01%
PreSGPRs: 14357 -> 14342 (-0.10%); split: -0.37%, +0.26%
VALU: 298325 -> 298347 (+0.01%); split: -0.01%, +0.02%
SALU: 57288 -> 57577 (+0.50%); split: -0.20%, +0.70%
SMEM: 18768 -> 18967 (+1.06%); split: -0.01%, +1.07%

fossil-db (navi21):
Totals from 239 (0.30% of 79825) affected shaders:
Instrs: 444783 -> 445177 (+0.09%); split: -0.07%, +0.15%
CodeSize: 2371776 -> 2373136 (+0.06%); split: -0.13%, +0.19%
Latency: 4226478 -> 4219221 (-0.17%); split: -0.24%, +0.07%
InvThroughput: 1430962 -> 1428445 (-0.18%); split: -0.23%, +0.06%
SClause: 9357 -> 9398 (+0.44%); split: -0.20%, +0.64%
Copies: 42742 -> 42927 (+0.43%); split: -0.53%, +0.96%
Branches: 12975 -> 12970 (-0.04%); split: -0.05%, +0.02%
PreSGPRs: 14368 -> 14312 (-0.39%); split: -0.47%, +0.08%
VALU: 306642 -> 306720 (+0.03%); split: -0.02%, +0.05%
SALU: 63702 -> 63790 (+0.14%); split: -0.31%, +0.45%
SMEM: 20030 -> 20231 (+1.00%); split: -0.00%, +1.01%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14458
Backport-to: 25.3
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38903>
 2025-12-12 13:58:42 +00:00
Rhys Perry
49d923078f ac/nir: fix calculation of aligned_new_size 
This should consider nir_round_up_components().

fossil-db (gfx1201):
Totals from 90 (0.11% of 79839) affected shaders:
MaxWaves: 1829 -> 1901 (+3.94%)
Instrs: 410780 -> 411825 (+0.25%); split: -0.02%, +0.27%
CodeSize: 2227956 -> 2234464 (+0.29%); split: -0.02%, +0.31%
VGPRs: 6952 -> 6760 (-2.76%); split: -3.11%, +0.35%
Latency: 3071765 -> 3073960 (+0.07%); split: -0.00%, +0.07%
InvThroughput: 766201 -> 767322 (+0.15%); split: -0.00%, +0.15%
VClause: 7887 -> 7898 (+0.14%); split: -0.08%, +0.22%
Copies: 48189 -> 48324 (+0.28%); split: -0.05%, +0.33%
PreVGPRs: 6605 -> 6595 (-0.15%); split: -0.18%, +0.03%
VALU: 237272 -> 238147 (+0.37%); split: -0.01%, +0.37%
SALU: 48987 -> 49003 (+0.03%)
VMEM: 15542 -> 15560 (+0.12%)
VOPD: 188 -> 200 (+6.38%)

fossil-db (navi31):
Totals from 89 (0.11% of 79825) affected shaders:
MaxWaves: 1811 -> 1883 (+3.98%)
Instrs: 403695 -> 404691 (+0.25%); split: -0.01%, +0.26%
CodeSize: 2150612 -> 2154860 (+0.20%); split: -0.03%, +0.23%
VGPRs: 6892 -> 6676 (-3.13%)
Latency: 3306107 -> 3310010 (+0.12%); split: -0.01%, +0.13%
InvThroughput: 813092 -> 814382 (+0.16%); split: -0.00%, +0.16%
VClause: 7999 -> 8010 (+0.14%); split: -0.06%, +0.20%
Copies: 50089 -> 50210 (+0.24%); split: -0.05%, +0.29%
PreVGPRs: 6596 -> 6586 (-0.15%); split: -0.18%, +0.03%
VALU: 239617 -> 240392 (+0.32%); split: -0.01%, +0.33%
SALU: 45349 -> 45363 (+0.03%)
VMEM: 15762 -> 15780 (+0.11%)
VOPD: 258 -> 262 (+1.55%)

fossil-db (navi21):
Totals from 89 (0.11% of 79825) affected shaders:
Instrs: 345634 -> 346426 (+0.23%); split: -0.00%, +0.23%
CodeSize: 1895616 -> 1900156 (+0.24%); split: -0.00%, +0.24%
Latency: 3043334 -> 3046859 (+0.12%); split: -0.01%, +0.13%
InvThroughput: 928236 -> 929626 (+0.15%); split: -0.01%, +0.16%
VClause: 7894 -> 7905 (+0.14%); split: -0.06%, +0.20%
Copies: 48694 -> 48785 (+0.19%); split: -0.03%, +0.22%
PreVGPRs: 6580 -> 6570 (-0.15%); split: -0.18%, +0.03%
VALU: 228323 -> 229072 (+0.33%); split: -0.01%, +0.33%
SALU: 47202 -> 47216 (+0.03%)
VMEM: 16546 -> 16564 (+0.11%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14458
Backport-to: 25.3
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38903>
 2025-12-12 13:58:42 +00:00
Marek Olšák
9bd2c6dcb2 ac/nir: allow smaller workgroups for GS
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It's not good for performance, but it's possible to use for debugging.
Running single-wave GS workgroups could work around any LDS race conditions.

Setting the workgroup size to 64 reliably works around
GLCTS *primitive_counter*line failures, indicating streamout data
corruption with multi-wave GS workgroups.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38328>
 2025-12-12 04:27:32 +00:00
Emma Anholt
10ba7675c8 nir/uub: Use an optional max_samples from drivers for sample counts. 
This triggers some unrolling in Fallout 4, GTAV, and Rocky Planet in my
shader-db.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38585>
 2025-12-11 14:26:11 +00:00
Marek Olšák
308da55f1a radv,radeonsi: use FRAG_RESULT_DUAL_SRC_BLEND 
this is slightly nicer

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38604>
 2025-12-10 19:16:46 +00:00
Arcady Goldmints-Orlov
0df8aa940c nir: Use nir_shader_intrinsics_pass in nir_lower_io_to_scalar
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Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38816>
 2025-12-05 22:30:22 +00:00
Yogesh Mohan Marimuthu
f27b2b8d77 winsys/amdgpu,ac: get eop and csa size,alignment from kernel query
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:21 +00:00
Yogesh Mohan Marimuthu
f322bc8631 ac: update amdgpu_drm.h for uq metadata query info 
struct drm_amdgpu_info_uq_fw_areas is renamed to drm_amdgpu_info_uq_metadata.
query infor structure for compute and sdma is added.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38647>
 2025-12-04 16:34:20 +00:00
Marek Olšák
9b011a7344 amd: rename most GFX115x definitions for released chips 
addrlib changes match the original code.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38718>
 2025-12-03 13:29:07 +00:00
Marek Olšák
e6499fa73e nir/recompute_io_bases: move color input bases after all other inputs 
This is related to the FS prolog.
It should have no effect on other drivers.

v2: make it optional via io_options

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38599>
 2025-11-29 05:00:40 +00:00
Marek Olšák
fa0bea5ff8 nir: remove nir_io_add_const_offset_to_base
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nir_opt_constant_folding does it now.

Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38277>
 2025-11-29 00:16:38 +00:00
Marek Olšák
21cdbfa223 ac,radv: move opt_vectorize_callback to common code
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radeonsi will use it.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38603>
 2025-11-28 20:16:10 +00:00
Marek Olšák
2c9995a94f ac/nir: move aco_nir_op_supports_packed_math_16bit here 
aco_nir_op_supports_packed_math_16bit currently can't be used by amd/common
because tests don't link with ACO, so linking would fail, but we want
to move the nir_opt_vectorize callback here that uses it.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38603>
 2025-11-28 20:16:10 +00:00
Samuel Pitoiset
5fd7af9e42 ac/surface: do not use tile swizzle for replayable/aliased FMASK surfaces 
Otherwise the VA might change.

Fixes: 2bbc7d1db6 ("radv: move more surf_index logic to use_tile_swizzle")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38696>
 2025-11-28 07:39:33 +00:00
Marek Olšák
d9d3f6703c ac,winsys/amdgpu: report why ac_query_gpu_info failed 
only these case were not reporting anything

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38602>
 2025-11-25 21:17:35 +00:00
Marek Olšák
1c3e7e4ca0 ac: document RELEASE_MEM limitation with PS_DONE/CS_DONE on gfx6-11 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38602>
 2025-11-25 21:17:35 +00:00
Benjamin Cheng
6aabc3d5d2 ac/parse_ib: Implement VCN dec message parsing 
This makes the IB dumps more useful for decode, as most of the actual
decode command is within the message buffers.

Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38631>
 2025-11-25 19:17:12 +00:00
Timur Kristóf
f00abaa1d4 ac/gpu_info: Add different sparse features 
The following sparse features are not supported by all GPUs, so
keep track of their support individually:
has_sparse_image_3d
has_sparse_image_standard_3d
has_sparse_unaligned_mip_size

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38553>
 2025-11-25 10:38:45 +01:00
Timur Kristóf
c15f9e7022 ac/surface: Use ADDR_TM_PRT_TILED_THIN1 on GFX6-8 
Don't use ADDR_TM_PRT_2D_TILED_THIN1 because it is not supported
on CI/VI according to CiLib::HwlOverrideTileMode, and it is also
missing from SiLib::HwlOverrideTileMode.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38553>
 2025-11-25 10:38:45 +01:00
Timur Kristóf
292460670a ac/gpu_info: Fix determining when CP DMA supports sparse 
Change has_cp_dma_with_null_prt_bug to cp_dma_supports_sparse
to know when CP DMA supports sparse. CP DMA doesn't support
sparse on any gfx6-9 chip.

Sources:
- d2669628 already documented this on gfx6 in 2018
- e259f405 added a radeonsi workaround for gfx9 in 2023
- 235f70e4 added a radv workaround for Polaris in 2025

Now RADV will use compute copy and fill for sparse resources
on all gfx6-9 chips (previously only did on Polaris and newer).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38553>
 2025-11-25 10:38:45 +01:00
Timur Kristóf
cd72ce3213 ac/gpu_info: Rename has_sparse_vm_mappings to has_sparse 
No functional changes. Just simplify the name.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38553>
 2025-11-25 10:38:44 +01:00
Daniel Schürmann
fc534ed209 amd: restrict radeon_info::marketing_name to 64 characters and copy it 
The pointer is owned by the DRM device.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38546>
 2025-11-24 12:34:08 +00:00
Daniel Schürmann
5a39e1e645 amd: remove radeon_info::is_pro_graphics 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38546>
 2025-11-24 12:34:08 +00:00
Daniel Schürmann
24a43666e3 amd: replace uses of radeon_info::name with ac_get_family_name() 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38546>
 2025-11-24 12:34:08 +00:00
Daniel Schürmann
7b2f88b97c amd: remove radeon_info::lowercase_name 
It is redundant.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38546>
 2025-11-24 12:34:08 +00:00
Daniel Schürmann
8777894d3e amd: remove radeon_info::dev_filename 
Instead, we can pass the file descriptor to ac_print_gpu_info().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38546>
 2025-11-24 12:34:08 +00:00
Samuel Pitoiset
108d2d29a9 ac,radv,radeonsi: add more SPM helpers to common code 
This also fixes a small bug on RADV for RDNA3 where counters might be
stuck.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38577>
 2025-11-24 08:05:08 +00:00