Commit graph

72 commits

Author SHA1 Message Date
Marek Olšák
cecc068774 gallium/radeon: allow VRAM-only placements again on APUs & recent amdgpu
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-01-30 13:27:14 +01:00
Marek Olšák
bf4d102ea3 gallium/radeon: add radeon_surf::is_linear
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-01 22:33:13 +01:00
Nicolai Hähnle
e56e1f8119 gallium/radeon: use the new parent/child pools for transfers
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97894
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-10-05 15:42:07 +02:00
Marek Olšák
e43bd861e8 radeonsi: track buffer bind history
similar to gl_buffer_object::UsageHistory

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
2016-10-04 16:11:58 +02:00
Nicolai Hähnle
13cb41f666 radeon/video: don't use sub-allocated buffers
Cc: Christian König <christian.koenig@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97976
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-30 12:38:29 +02:00
Michel Dänzer
8d8c440ebf gallium/radeon: Initialize pipe_resource::next to NULL
Fixes lots of piglit tests crashing due to using uninitialized memory.

Fixes: ecd6fce261 ("mesa/st: support lowering multi-planar YUV")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-28 10:39:22 +09:00
Marek Olšák
5981ab5445 gallium: remove PIPE_BIND_TRANSFER_READ/WRITE
not used in any useful way

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2016-09-08 22:51:33 +02:00
Marek Olšák
e7a73b75a0 gallium: switch drivers to the slab allocator in src/util 2016-09-06 14:24:04 +02:00
Marek Olšák
0d2e43fcb1 gallium/radeon: derive buffer placement and flags only at initialization
Invalidated buffers don't have to go through it.

Split r600_init_resource into r600_init_resource_fields and
r600_alloc_resource.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-09-05 18:01:15 +02:00
Marek Olšák
f4b977bf3d gallium/radeon: add r600_resource::vram_usage and gart_usage
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-08-06 13:56:14 +02:00
Marek Olšák
700de07771 radeonsi: implement buffer_subdata without indirect calls
There is less noise in CPU profile data now.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-07-23 13:33:42 +02:00
Marek Olšák
1ffe77e7bb gallium: split transfer_inline_write into buffer and texture callbacks
to reduce the call indirections with u_resource_vtbl.

The worst call tree you could get was:
  - u_transfer_inline_write_vtbl
    - u_default_transfer_inline_write
      - u_transfer_map_vtbl
        - driver_transfer_map
      - u_transfer_unmap_vtbl
        - driver_transfer_unmap

That's 6 indirect calls. Some drivers only had 5. The goal is to have
1 indirect call for drivers that care. The resource type can be determined
statically at most call sites.

The new interface is:
  pipe_context::buffer_subdata(ctx, resource, usage, offset, size, data)
  pipe_context::texture_subdata(ctx, resource, level, usage, box, data,
                                stride, layer_stride)

v2: fix whitespace, correct ilo's behavior

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Acked-by: Roland Scheidegger <sroland@vmware.com>
2016-07-23 13:33:42 +02:00
Marek Olšák
7db10093d3 gallium/radeon: boolean -> bool, TRUE -> true, FALSE -> false
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-06-25 23:13:42 +02:00
Marek Olšák
d5383a7d31 gallium/radeon: use r600_resource_reference
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-06-25 23:13:42 +02:00
Marek Olšák
d5491a81ff gallium/radeon: don't use the DMA ring for pipelined buffer uploads
Submitting a DMA IB flushes the GFX IB and all GPU caches.

Vedran Miletić said:
  "On Tonga 380X, this improves The Talos Principle from 8.3 fps to 28.3 fps
   (all graphics settings Ultra, 4xAA, 1080p resolution with downsampling
   from 1200p)."

Some anonymous dude said:
   R9 390 results:
      Tomb Raider (normal settings): 80 -> 88 FPS
      Talos Principle (custom settings): 23 -> 56 FPS
      Metro Last Light Redux (default benchmark settings): 39 -> 40 FPS

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Tested-by: Vedran Miletić <vedran@miletic.net>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2016-06-04 15:42:33 +02:00
Marek Olšák
f330b7a14f gallium/radeon: handle VRAM_GTT placements as having slow CPU reads
not sure if we should include GTT WC too

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-05-19 12:35:50 +02:00
Nicolai Hähnle
0558564200 gallium/radeon: add radeon_emitted to check for non-trivial IBs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-17 15:28:39 -05:00
Nicolai Hähnle
562c4a17b7 winsys/radeon: remove use_reusable_pool parameter from buffer_create
All callers set this parameter to true.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-27 11:16:41 -05:00
Nicolai Hähnle
13acf2b243 gallium/radeon: remove use_reusable_pool parameter from r600_init_resource
All callers set it to true.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-27 11:16:41 -05:00
Nicolai Hähnle
a17911ceb1 gallium/radeon: handle failure when mapping staging buffer
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-04-14 16:29:23 -05:00
Marek Olšák
5b6a0b7fc0 gallium/radeon: set GTT WC on tiled textures
Just for consistency. This should have no effect, because OpenGL textures
always go to VRAM.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-04-12 14:29:48 +02:00
Marek Olšák
5a4b74d1ba gallium/radeon: relax requirements on VRAM placements on APUs
This makes Tonga with vramlimit=128 2x faster in Heaven.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-04-12 14:29:48 +02:00
Marek Olšák
1dd8832e04 gallium/radeon: allow allocating textures >= 4 GB
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-04-12 14:29:48 +02:00
Marek Olšák
7e78b5ed38 pb_buffer: switch pb_buffer::size to 64 bits
being able to allocate more than 4 GB may be useful

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-04-12 14:29:47 +02:00
Marek Olšák
6b187bbd9f gallium/radeon: disallow reallocation of shared buffers
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-09 15:02:26 +01:00
Marek Olšák
ecbd3aba17 gallium/radeon: if we can't discard a whole resource, discard the range instead
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-09 15:02:26 +01:00
Marek Olšák
afdaffcbdb gallium/radeon: buffer valid range tracking only works with unshared buffers
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-09 15:02:26 +01:00
Marek Olšák
f914779c75 gallium/radeon: set texture metadata only once
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-09 15:02:26 +01:00
Marek Olšák
3146014d5f gallium/radeon: don't use temporary buffers for persistent mappings
Cc: 11.1 11.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-03-08 20:08:52 +01:00
Marek Olšák
1e864d7379 gallium/radeon: rename & reorder members of radeon_info
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2016-02-05 17:28:00 +01:00
Michel Dänzer
ad20be1f30 gallium/radeon: Rename do_invalidate_resource to invalidate_buffer
And only call it from r600_invalidate_resource for buffer resources.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-18 17:39:37 +09:00
Nicolai Hähnle
e976860638 gallium/radeon: do not reallocate user memory buffers
The whole point of AMD_pinned_memory is that applications don't have to map
buffers via OpenGL - but they're still allowed to, so make sure we don't break
the link between buffer object and user memory unless explicitly instructed
to.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:41:24 -05:00
Nicolai Hähnle
321140d563 gallium/radeon: implement PIPE_CAP_INVALIDATE_BUFFER
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:41:04 -05:00
Nicolai Hähnle
08c71740ad gallium/radeon: reset valid_buffer_range on PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE
This accomodates a streaming pattern where the discard flag is set when the
application wraps back to the beginning of the buffer.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-14 09:40:00 -05:00
Marek Olšák
020009f7cc u_upload_mgr: pass alignment to u_upload_alloc manually
The fixed alignment of u_upload_mgr will go away.
This is the first step.

The motivation is that one u_upload_mgr can have multiple users,
each allocating from the same buffer, but requiring a different alignment.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-02 15:15:44 +01:00
Marek Olšák
cf811faeff gallium/radeon: remove radeon_winsys_cs_handle
"radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf".

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák
6cc8f6c6a7 gallium/radeon: inline the r600_rings structure
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2015-11-13 19:54:41 +01:00
Bas Nieuwenhuizen
afa357c3b0 radeonsi: Allocate buffers for DCC.
As the alignment requirements can be 32 KiB or more, also adding
an aligned buffer creation function.

DCC is disabled for textures that can be shared as sharing the
DCC buffers has not been implemented yet.

Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-10-24 00:42:01 +02:00
Marek Olšák
282b378012 gallium/radeon: handle buffer_map staging buffer failures better
Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-09-24 19:51:42 +02:00
Marek Olšák
b409524fef gallium/radeon: handle PIPE_TRANSFER_FLUSH_EXPLICIT
Basically, do the same thing as for buffer_unmap, but use the explicit range
instead. It's for apps which want to map a whole buffer and mark touched
ranges explicitly.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-09-10 17:14:15 +02:00
Marek Olšák
8ba70e0a74 radeonsi: fix DRM version checks for amdgpu DRM 3.0.0 2015-08-14 15:02:29 +02:00
Marek Olšák
7e5d56394b gallium/radeon: add a debug flag not to use write combining (v2)
v2: just clear the flag before the allocation

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-08-10 18:26:44 +02:00
Marek Olšák
592ce6e2d1 gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface
The timeout parameter covers both cases.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-07 00:06:13 +02:00
Marek Olšák
7713d594e4 r600g,radeonsi: implement GL_AMD_pinned_memory
v2: update release notes

Reviewed-by: Christian König <christian.koenig@amd.com>
2015-02-17 17:31:48 +01:00
Marek Olšák
218b15715e radeonsi: initialize TC_L2_dirty to false after buffer allocation
I forgot to do this, though "true" should have no effect on correctness.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-02-17 17:31:48 +01:00
Michel Dänzer
7b4276d7ac r600g,radeonsi: Always use GTT again for PIPE_USAGE_STREAM buffers
Putting those in VRAM can cause long pauses due to buffers being moved
into / out of VRAM.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84662
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2014-10-09 18:11:44 +09:00
Michel Dänzer
5679ccfcaf r600g,radeonsi: Set RADEON_GEM_NO_CPU_ACCESS flag for tiled BOs
This lets the kernel know that such BOs can be pinned outside of the CPU
accessible part of VRAM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-10 12:01:10 +09:00
Michel Dänzer
2adf7ee92e r600g,radeonsi: Preserve existing buffer flags
The default case was accidentally clearing RADEON_FLAG_CPU_ACCESS from the
previous fall-through cases.

Reported-by: Mathias Fröhlich <Mathias.Froehlich@gmx.net>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-03 12:49:59 +09:00
Michel Dänzer
51131c423c r600g,radeonsi: Inform the kernel if a BO will likely be accessed by the CPU
This allows the kernel to prevent such BOs from ever being stored in the
CPU inaccessible part of VRAM.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-09-02 15:24:07 +09:00
Niels Ole Salscheider
5ae9bdafd4 gallium/radeon: Do not use u_upload_mgr for buffer downloads
Instead create a staging texture with pipe_buffer_create and
PIPE_USAGE_STAGING.

u_upload_mgr sets the usage of its staging buffer to PIPE_USAGE_STREAM.
But since 150ac07b85 CPU -> GPU streaming buffers
are created in VRAM. Therefore the staging texture (in VRAM) does not offer any
performance improvements for buffer downloads.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2014-08-19 12:56:04 +02:00