fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-04-23 03:00:37 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

gallium/radeon: add radeon_surf::is_linear

Browse source 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-26 13:42:28 +02:00
parent e9c76eeeaa
commit bf4d102ea3
8 changed files with 15 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/gallium/drivers/radeon/r600_buffer_common.c
View file

@ -160,7 +160,7 @@ void r600_init_resource_fields(struct r600_common_screen *rscreen,
/* Tiled textures are unmappable. Always put them in VRAM. */
if (res->b.b.target != PIPE_BUFFER &&
rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) {
!rtex->surface.is_linear) {
res->domains = RADEON_DOMAIN_VRAM;
res->flags &= ~RADEON_FLAG_CPU_ACCESS;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS |

8
src/gallium/drivers/radeon/r600_test_dma.c
View file

@ -331,8 +331,8 @@ void r600_test_dma(struct r600_common_screen *rscreen)
dstz = rand() % (tdst.array_size - depth + 1);
/* special code path to hit the tiled partial copies */
if (rsrc->surface.level[0].mode >= RADEON_SURF_MODE_1D &&
rdst->surface.level[0].mode >= RADEON_SURF_MODE_1D &&
if (!rsrc->surface.is_linear &&
!rdst->surface.is_linear &&
rand() & 1) {
if (max_width < 8 || max_height < 8)
continue;
@ -359,8 +359,8 @@ void r600_test_dma(struct r600_common_screen *rscreen)
}
/* special code path to hit out-of-bounds reads in L2T */
if (rsrc->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED &&
rdst->surface.level[0].mode >= RADEON_SURF_MODE_1D &&
if (rsrc->surface.is_linear &&
!rdst->surface.is_linear &&
rand() % 4 == 0) {
srcx = 0;
srcy = 0;

8
src/gallium/drivers/radeon/r600_texture.c
View file

@ -425,7 +425,7 @@ static void r600_degrade_tile_mode_to_linear(struct r600_common_context *rctx,
return;
if (rtex->resource.is_shared ||
rtex->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
rtex->surface.is_linear)
return;
/* This fails with MSAA, depth, and compressed textures. */
@ -1406,7 +1406,7 @@ static void r600_texture_invalidate_storage(struct r600_common_context *rctx,
/* There is no point in discarding depth and tiled buffers. */
assert(!rtex->is_depth);
assert(rtex->surface.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED);
assert(rtex->surface.is_linear);
/* Reallocate the buffer in the same pipe_resource. */
r600_alloc_resource(rscreen, &rtex->resource);
@ -1465,7 +1465,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
* Use the staging texture for uploads if the underlying BO
* is busy.
*/
if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D)
if (!rtex->surface.is_linear)
use_staging_texture = true;
else if (usage & PIPE_TRANSFER_READ)
use_staging_texture = (rtex->resource.domains &
@ -2446,7 +2446,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
}
/* only supported on tiled surfaces */
if (tex->surface.level[0].mode < RADEON_SURF_MODE_1D) {
if (tex->surface.is_linear) {
continue;
}

1
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -294,6 +294,7 @@ struct radeon_surf {
* the first level.
*/
unsigned num_dcc_levels:4;
unsigned is_linear:1;
uint32_t flags;
/* These are return values. Some of them can be set by the caller, but

5
src/gallium/drivers/radeonsi/si_blit.c
View file

@ -1012,7 +1012,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
info->src.box.width == dst_width &&
info->src.box.height == dst_height &&
info->src.box.depth == 1 &&
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
!dst->surface.is_linear &&
(!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
/* Check the last constraint. */
if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
@ -1116,8 +1116,7 @@ static void si_blit(struct pipe_context *ctx,
* resource_copy_region can't do this yet, because dma_copy calls it
* on failure (recursion).
*/
if (rdst->surface.level[info->dst.level].mode ==
RADEON_SURF_MODE_LINEAR_ALIGNED &&
if (rdst->surface.is_linear &&
sctx->b.dma_copy &&
util_can_blit_via_copy_region(info, false)) {
sctx->b.dma_copy(ctx, info->dst.resource, info->dst.level,

2
src/gallium/drivers/radeonsi/si_state.c
View file

@ -2360,7 +2360,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
sctx->framebuffer.compressed_cb_mask |= 1 << i;
}
if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
if (rtex->surface.is_linear)
sctx->framebuffer.any_dst_linear = true;
r600_context_add_resource_size(ctx, surf->base.texture);

1
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -566,6 +566,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
if (surf->htile_size && tex->last_level)
surf->htile_size *= 2;
surf->is_linear = surf->level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
return 0;
}

1
src/gallium/winsys/radeon/drm/radeon_drm_surface.c
View file

@ -178,6 +178,7 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
surf_ws->blk_w = surf_drm->blk_w;
surf_ws->blk_h = surf_drm->blk_h;
surf_ws->bpe = surf_drm->bpe;
surf_ws->is_linear = surf_drm->level[0].mode <= RADEON_SURF_MODE_LINEAR_ALIGNED;
surf_ws->flags = surf_drm->flags;
surf_ws->surf_size = surf_drm->bo_size;