Commit graph

13647 commits

Author SHA1 Message Date
Daniel Stone
59a7fc2054 ci/radeonsi: Occlusion queries are flaky on stoney
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26678>
2023-12-13 22:51:52 +00:00
Chris Spencer
9385f1d4e2 radv/android: Only limit advertised Vulkan version in strict mode
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Acked-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25101>
2023-12-13 20:09:37 +00:00
Marek Olšák
390f26eefb ac,radeonsi: require DRM 3.27+ (kernel 4.20+) same as RADV
The only major change is the code removal of the legacy BO list path
in the winsys, which required switching "debug_all_bos" to the new path.

Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26547>
2023-12-13 16:26:17 +00:00
Marek Olšák
5cfd659276 ac/llvm: remove code for converting txd from 1D to 2D because NIR does it
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26547>
2023-12-13 16:26:17 +00:00
Tatsuyuki Ishi
c3c3a8926a radv/amdgpu: Separate the concept of residency from use_global_list.
A BO can be always resident by two ways:
1. Through kernel bookkeeping. The BO is created with
   AMDGPU_GEM_CREATE_VM_ALWAYS_VALID and bo->is_local gets set to true.
2. Through the driver global BO list. On every submission, the global
   BO list is added to the CS's BO list.

Until now, use_global_list reflected either 1. or 2. . This commit
changes it to reflect 2. only, and update callsites that checks for
residency to use a new helper.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26591>
2023-12-13 12:03:20 +00:00
Tatsuyuki Ishi
63120a55b8 radv/amdgpu: Remove virtual bo dump logic.
Virtual BOs cannot go into the global bo list. Accessing bo_handle is
also invalid for virtual BOs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26592>
2023-12-13 11:42:35 +00:00
Samuel Pitoiset
ca8d9f850b radv/ci: remove dEQP-VK.mesh_shader.ext.query.* from the lists
meshShaderQueries has been recently disabled because it causes random
GPU hangs in CI, I'm still investigating it. But let's clean the CI
lists to avoid any confusion, I will re-introduce them if needed but
this issue can also be reproduced without mesh shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26651>
2023-12-13 08:33:24 +00:00
Samuel Pitoiset
f576ce3340 radv: advertise VK_KHR_vertex_attribute_divisor
This is a promotion from the EXT, except the new property
supportsNonZeroFirstInstance which should already be supported.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26595>
2023-12-13 08:08:21 +00:00
Samuel Pitoiset
0605631094 radv: stop clearing FMASK_COMPRESS_1FRAG_ONLY for TC-compat CMASK images
TC-compat CMASK means Fmask decompression isn't needed because the hw
can read it directly from shaders, so this shouldn't have any effects.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26575>
2023-12-13 07:48:51 +00:00
Samuel Pitoiset
c70c269b16 radv: remove useless check for TC-compat CMASK images during fb emission
The FMASK decompression only happens for images with FMASK and without
TC-compat CMASK, so both can never be TRUE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26575>
2023-12-13 07:48:51 +00:00
Friedrich Vock
f1817ab7e0 radv,vtn,driconf: Add and use radv_rt_ssbo_non_uniform workaround for Crysis 2/3 Remastered
Crysis 2 and 3 Remastered's RT shaders non-uniformly index into SSBO
descriptor arrays without specifying the NonUniformEXT qualifier on the
relevant access chains/load ops. This leads to artifacts around objects.

To add insult to injury, the game fails to provide a meaningful
applicationName/engineName in the Vulkan part of the DX11-Vulkan interop
solution used for RT. Both of these fields are set to "nvpro-sample"
(perhaps the code has been copied from NVIDIA's sample applications).
Therefore, fall back to executable name matching.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9883
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26391>
2023-12-12 21:16:39 +00:00
Daniel Schürmann
dd7b6898e6 radv: fix number of physical SGPRs on GFX10+
This change has no effect.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26521>
2023-12-11 10:39:51 +00:00
Daniel Schürmann
5ebba87772 aco: rename max_wave64_per_simd -> max_waves_per_simd
and update usage. Changes are because the scheduler targets
a different number of waves.

Totals from 195 (0.25% of 79330) affected shaders: (GFX11)

MaxWaves: 3120 -> 3108 (-0.38%)
Instrs: 71202 -> 71070 (-0.19%); split: -0.27%, +0.09%
CodeSize: 383272 -> 382828 (-0.12%); split: -0.21%, +0.10%
VGPRs: 7392 -> 7752 (+4.87%)
Latency: 2280141 -> 2262487 (-0.77%); split: -0.79%, +0.02%
InvThroughput: 4759022 -> 5725442 (+20.31%); split: -0.01%, +20.32%
VClause: 1737 -> 1741 (+0.23%); split: -3.11%, +3.34%
SClause: 2385 -> 2376 (-0.38%); split: -0.80%, +0.42%
Copies: 5257 -> 5274 (+0.32%); split: -0.25%, +0.57%
Branches: 1213 -> 1212 (-0.08%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26521>
2023-12-11 10:39:50 +00:00
Daniel Schürmann
f5bdc46a57 amd: rename max_wave64_per_simd -> max_waves_per_simd
These are hard limits and don't depend on wave size.
Accordingly, also update the usage in order to avoid
reporting unreasonable occupancy.

Totals from 192 (0.24% of 79330) affected shaders:

MaxWaves: 5814 -> 3072 (-47.16%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26521>
2023-12-11 10:39:50 +00:00
Samuel Pitoiset
ac20c70e9d radv: promote EXT_calibrated_timestamps to KHR
All functionality are similar.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26596>
2023-12-11 08:26:20 +01:00
Timur Kristóf
8e77da1f21 radv: Implement vkCmdUpdateBuffer on transfer queues.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26580>
2023-12-09 01:49:13 +00:00
Timur Kristóf
635c81f723 radv: Implement buffer copies on transfer queues.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26580>
2023-12-09 01:49:13 +00:00
Timur Kristóf
a632024700 radv: Implement vkCmdWriteBufferMarker2AMD on transfer queues.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26580>
2023-12-09 01:49:13 +00:00
Timur Kristóf
7a4f535145 radv: Implement vkCmdWriteTimestamp2 on transfer queues.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26580>
2023-12-09 01:49:13 +00:00
Timur Kristóf
32dd77ea2d radv: Implement vkCmdFillBuffer on transfer queues.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26580>
2023-12-09 01:49:13 +00:00
Timur Kristóf
23590a4e98 radv: Implement barriers for transfer queues.
The current flush flags in RADV don't really match the SDMA HW,
so just always emit a NOP packet, for now.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26580>
2023-12-09 01:49:13 +00:00
Marek Olšák
2f281b39ab ac/gpu_info: fix printing radeon_info after adding VPE
Fixes: 3ec397819e - amd: add new hardware ip for vpe

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-09 00:05:28 +00:00
Marek Olšák
00dd4d400e ac,radeonsi: rename pos_inputs -> fragcoord_components
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26307>
2023-12-09 00:05:27 +00:00
Timur Kristóf
1c8c3e5a7a radv: Don't retile DCC on transfer queues.
Instead, the retile will be executed on another queue type
when the image is transitioned to another queue.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25834>
2023-12-08 14:46:17 +00:00
Timur Kristóf
5c30d462b9 radv: Disable HTILE on exclusive images with transfer queues when SDMA doesn't support it.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25834>
2023-12-08 14:46:17 +00:00
Timur Kristóf
1764259ba8 radv: Disable DCC on exclusive images with transfer queue when SDMA doesn't support it.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25834>
2023-12-08 14:46:17 +00:00
Timur Kristóf
89a6b08cba radv: disable HTILE/DCC for concurrent images with transfer queue if unsupported.
DCC and HTILE are only supported by SDMA on GFX10+ (unless disabled by a workaround).

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25834>
2023-12-08 14:46:16 +00:00
Chia-I Wu
ad6b6673be radv: convert a check in radv_get_memory_fd to assert
VUID-VkBindImageMemoryInfo-memory-02628 and
VUID-VkBindImageMemoryInfo-memory-02629 make sure the memory offset is 0
for dedicated allocations.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25964>
2023-12-08 14:21:42 +00:00
Chia-I Wu
8aa62ba240 radv: fix asserts for radv_init_metadata
radv_init_metadata hits several assert failures when the image is
multi-planar.  Make sure we use plane 0.

This change should make no difference in practice.  Also, this is done
only to follow radeonsi.  Since the opaque metadata is mainly for
validations and DCC, and we don't enable DCC for multi-planar images, we
probably don't need to call radv_query_opaque_metadata at all.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25964>
2023-12-08 14:21:42 +00:00
Chia-I Wu
035cf7ab97 radv: fix a typo in radv_image_view_make_descriptor
Only GFX8 and before have legacy_surf_level.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25964>
2023-12-08 14:21:42 +00:00
Chia-I Wu
07f575a8a6 radv: fix VkSubresourceLayout2KHR for multi-planar formats with modifiers
Memory planes and format planes are equivalent for multi-planar formats
with modifiers.  Do not return the DCC info of plane 0.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25964>
2023-12-08 14:21:42 +00:00
Chia-I Wu
8f60ccf969 radv: fix VkDrmFormatModifierProperties2EXT for multi-planar formats
Do not report DCC modifiers for multi-planar formats.  We don't support
DCC for them and drmFormatModifierPlaneCount had incorrect values.

Fix vkGetImageSubresourceLayout for multi-planar images with modifiers.
In that case, memory planes and format planes are equivalent.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25964>
2023-12-08 14:21:42 +00:00
Samuel Pitoiset
90dda31901 radv: simplify disabling MRT compaction for PS epilogs
If the fragment shader isn't compiled, the PS epilog key isn't used
at all with GPL.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26563>
2023-12-08 13:52:40 +00:00
Juston Li
dc7c1d989b radv: enable stippledBresenhamLines on GFX9 chips
This isn't supposed to work nor does it match radeonsi but setting
AUTO_RESET_CNTL=0 by default for GFX9 chips is what gets it passing
linestrip CTS tests:

dEQP-VK.rasterization.primitives.dynamic_stipple.bresenham_line_strip
dEQP-VK.rasterization.primitives.dynamic_stipple_and_topology.bresenham_line_strip
dEQP-VK.rasterization.primitives.dynamic_stipple_and_topology.bresenham_line_strip_wide
dEQP-VK.rasterization.primitives.static_stipple.bresenham_line_strip

Signed-off-by: Juston Li <justonli@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24623>
2023-12-07 19:10:15 +00:00
Tatsuyuki Ishi
b2e8095d6d radv: Add workaround to allow sparse binding on gfx queues.
For working around improper usage of sparse in DOOM Eternal.

When fully explicit sync sparse binding is implemented, this path will
remain implicit sync to also deal with the improper semaphore usage.
radv_queue_submit_bind_sparse_memory will likely get a bool parameter to
control explicit / implicit sync in that case.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26464>
2023-12-07 11:40:38 +00:00
Yonggang Luo
72e30c8853 treewide: Avoid use align as variable, replace it with other names
align is a function and when we want use it, the align variable will shadow it
So replace it with other names

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25997>
2023-12-07 02:30:53 +00:00
Faith Ekstrand
09fc5e1c4d nir: Split has_[su]dot_4x8 bits into regular and _sat versions
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26533>
2023-12-06 23:15:33 +00:00
Samuel Pitoiset
47f666b64b radv: enable extendedDynamicState3AlphaToCoverageEnable on GFX11
This is now supported and this allows Zink to enable full ds3 mode for
even less stuttering. DXVK also uses dynamic alpha to coverage
sometimes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26250>
2023-12-06 16:36:16 +00:00
Samuel Pitoiset
bca4ebc3c4 radv: export MRTZ via PS epilogs when alpha to coverage is dynamic on GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26250>
2023-12-06 16:36:16 +00:00
Samuel Pitoiset
79cf2b6824 radv: determine and emit SPI_SHADER_Z_FORMAT for PS epilogs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
4248d0b03a radv,aco: declare PS epilog VGPR arguments for depth/stencil/samplemask
Depth/stencil/samplemask inputs are first to match
create_fs_jump_to_epilog().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
8b87c985b0 radv: prepare the PS epilog key for exporting MRTZ on RDNA3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
5b01285cfb radv: determine if MRTZ needs to be exported via PS epilogs
For GFX11 only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
b2a37b4304 ac/nir: add an option to skip MRTZ exports in ac_nir_lower_ps()
On RDNA3, alpha to coverage needs to be exported through MRTZ when
depth, stencil or samplemask are also exported. This option will allow
us to export MRTZ from PS epilogs instead of the main FS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Samuel Pitoiset
81eeb157f8 aco: export depth/stencil/samplemask in create_fs_jump_to_epilog()
This currently has no effects because the store_output instructions
are removed earlier (in ac_nir_lower_ps). Though, this will be needed
for exporting MRTZ from PS epilogs for alpha to coverage on RDNA3.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26413>
2023-12-06 11:49:31 +00:00
Eric Engestrom
90a77f55de ci: drop containers, builds, and tests from post-merge pipeline
All these jobs are redundant and a waste of resources:
- the containers have already been built & pushed in the merge pipeline
- the mesa build variants have already all passed
- the driver tests have already all passed

None of these jobs are doing anything useful in this pipeline, but it
costs a factor of 2x to our infrastructure, so let's remove them.

In other words, the only job left in the post-merge pipeline is the
`pages` job that deploys the update to the website.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26451>
2023-12-06 08:26:04 +00:00
Samuel Pitoiset
a3b3a7d36a radv: remove unused code for compiling PS epilogs as part of pipelines
Since we switched to the "on-demand" path for GPL, this is dead code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
2023-12-06 08:01:46 +00:00
Samuel Pitoiset
725fc0ec03 radv: switch to on-demand PS epilogs for GPL
RADV currently has two paths for PS epilogs:
- the first one is mostly used by GPL to compile fragment shader epilogs
  as part of the graphics pipeline. It's supposed to be optimal because
  fragment shader epilogs are compiled in the pipeline and eventually
  cached.
- the second one (the "on-demand" path) is required when some dynamic
  states are used because otherwise it's just impossible to compile the
  fragment shader. These epilogs are compiled during cmdbuf recording
  when all needed info are known, they are also cached in memory. This
  is the main path for Zink.

Having two different paths isn't ideal for maintenance but there is
another problem. On RDNA3, alpha to coverage needs to be exported as
part of MRTZ when either depth/stencil/samplemask are exported. The
problem being that with GPL, the PSO multisample state can be NULL when
the frag shader lib is created, which means that we can't know if atc
needs to be exported or not, even if it's static. The solution seems to
to always use on-demand fragment shader epilogs for GPL on RDNA3.

So far, I think that switching to on-demand PS epilogs unconditionally
for GPL shouldn't hurt performance and that will simplify a lot of
things.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
2023-12-06 08:01:45 +00:00
Qiang Yu
7656251294 aco: fix set_wqm segfault when ps prolog
ps prolog does not have nir shader.

Fixes: 3b10547e67 ("aco: enable helper lanes if shader->info.fs.require_full_quads")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26512>
2023-12-06 05:34:30 +00:00
Eric Engestrom
df8ea977be radeonsi/ci: track changes to vpelib
According to `src/amd/meson.build`, radeonsi uses vpelib, so we should
track changes to it as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26479>
2023-12-06 01:58:41 +00:00