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radv: remove unused code for compiling PS epilogs as part of pipelines

Browse source 
Since we switched to the "on-demand" path for GPL, this is dead code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26398>
This commit is contained in:
Samuel Pitoiset 2023-11-29 17:39:52 +01:00 • committed by Marge Bot
parent 725fc0ec03
commit a3b3a7d36a
6 changed files with 22 additions and 140 deletions
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16
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1680,11 +1680,6 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer, bool first_stage_only)
if (mask & RADV_PREFETCH_PS) {
radv_emit_shader_prefetch(cmd_buffer, cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]);
if (cmd_buffer->state.ps_epilog) {
struct radv_shader_part *ps_epilog = cmd_buffer->state.ps_epilog;
si_cp_dma_prefetch(cmd_buffer, ps_epilog->va, ps_epilog->code_size);
}
}
state->prefetch_L2_mask &= ~mask;
@ -6529,7 +6524,6 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline
}
cmd_buffer->state.gs_copy_shader = graphics_pipeline->base.gs_copy_shader;
cmd_buffer->state.ps_epilog = graphics_pipeline->ps_epilog;
cmd_buffer->state.last_vgt_shader = graphics_pipeline->base.shaders[graphics_pipeline->last_vgt_api_stage];
cmd_buffer->state.graphics_pipeline = graphics_pipeline;
@ -8838,12 +8832,10 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
if (cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT] &&
cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]->info.has_epilog) {
if (cmd_buffer->state.ps_epilog) {
ps_epilog = cmd_buffer->state.ps_epilog;
} else if ((cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline ||
(cmd_buffer->state.dirty &
(RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK | RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE | RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_EQUATION)))) {
if ((cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline ||
(cmd_buffer->state.dirty &
(RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_MASK | RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_ENABLE |
RADV_CMD_DIRTY_DYNAMIC_ALPHA_TO_COVERAGE_ENABLE | RADV_CMD_DIRTY_DYNAMIC_COLOR_BLEND_EQUATION)))) {
ps_epilog = lookup_ps_epilog(cmd_buffer);
if (!ps_epilog) {
vk_command_buffer_set_error(&cmd_buffer->vk, VK_ERROR_OUT_OF_HOST_MEMORY);

61
src/amd/vulkan/radv_pipeline_cache.c
View file

@ -230,9 +230,7 @@ struct radv_pipeline_cache_object {
struct vk_pipeline_cache_object base;
unsigned num_shaders;
unsigned num_stack_sizes;
unsigned ps_epilog_binary_size;
struct radv_shader_part *ps_epilog;
void *data; /* pointer to stack sizes or ps epilog binary */
void *data; /* pointer to stack sizes */
uint8_t sha1[SHA1_DIGEST_LENGTH];
struct radv_shader *shaders[];
};
@ -241,11 +239,10 @@ const struct vk_pipeline_cache_object_ops radv_pipeline_ops;
static struct radv_pipeline_cache_object *
radv_pipeline_cache_object_create(struct vk_device *device, unsigned num_shaders, const void *hash,
unsigned num_stack_sizes, unsigned ps_epilog_binary_size)
unsigned num_stack_sizes)
{
assert(num_stack_sizes == 0 || ps_epilog_binary_size == 0);
const size_t size = sizeof(struct radv_pipeline_cache_object) + (num_shaders * sizeof(struct radv_shader *)) +
ps_epilog_binary_size + (num_stack_sizes * sizeof(uint32_t));
(num_stack_sizes * sizeof(uint32_t));
struct radv_pipeline_cache_object *object = vk_alloc(&device->alloc, size, 8, VK_SYSTEM_ALLOCATION_SCOPE_CACHE);
if (!object)
@ -254,8 +251,6 @@ radv_pipeline_cache_object_create(struct vk_device *device, unsigned num_shaders
vk_pipeline_cache_object_init(device, &object->base, &radv_pipeline_ops, object->sha1, SHA1_DIGEST_LENGTH);
object->num_shaders = num_shaders;
object->num_stack_sizes = num_stack_sizes;
object->ps_epilog_binary_size = ps_epilog_binary_size;
object->ps_epilog = NULL;
object->data = &object->shaders[num_shaders];
memcpy(object->sha1, hash, SHA1_DIGEST_LENGTH);
memset(object->shaders, 0, sizeof(object->shaders[0]) * num_shaders);
@ -273,8 +268,6 @@ radv_pipeline_cache_object_destroy(struct vk_device *_device, struct vk_pipeline
if (pipeline_obj->shaders[i])
radv_shader_unref(device, pipeline_obj->shaders[i]);
}
if (pipeline_obj->ps_epilog)
radv_shader_part_unref(device, pipeline_obj->ps_epilog);
vk_pipeline_cache_object_finish(&pipeline_obj->base);
vk_free(&_device->alloc, pipeline_obj);
@ -289,11 +282,9 @@ radv_pipeline_cache_object_deserialize(struct vk_pipeline_cache *cache, const vo
unsigned total_size = blob->end - blob->current;
unsigned num_shaders = blob_read_uint32(blob);
unsigned num_stack_sizes = blob_read_uint32(blob);
unsigned ps_epilog_binary_size = blob_read_uint32(blob);
struct radv_pipeline_cache_object *object;
object =
radv_pipeline_cache_object_create(&device->vk, num_shaders, key_data, num_stack_sizes, ps_epilog_binary_size);
object = radv_pipeline_cache_object_create(&device->vk, num_shaders, key_data, num_stack_sizes);
if (!object)
return NULL;
@ -315,20 +306,9 @@ radv_pipeline_cache_object_deserialize(struct vk_pipeline_cache *cache, const vo
object->shaders[i] = container_of(shader, struct radv_shader, base);
}
const size_t data_size = ps_epilog_binary_size + (num_stack_sizes * sizeof(uint32_t));
const size_t data_size = num_stack_sizes * sizeof(uint32_t);
blob_copy_bytes(blob, object->data, data_size);
if (ps_epilog_binary_size) {
assert(num_stack_sizes == 0);
struct radv_shader_part_binary *binary = object->data;
object->ps_epilog = radv_shader_part_create(device, binary, device->physical_device->ps_wave_size);
if (!object->ps_epilog) {
vk_pipeline_cache_object_unref(&device->vk, &object->base);
return NULL;
}
}
return &object->base;
}
@ -339,12 +319,11 @@ radv_pipeline_cache_object_serialize(struct vk_pipeline_cache_object *object, st
blob_write_uint32(blob, pipeline_obj->num_shaders);
blob_write_uint32(blob, pipeline_obj->num_stack_sizes);
blob_write_uint32(blob, pipeline_obj->ps_epilog_binary_size);
for (unsigned i = 0; i < pipeline_obj->num_shaders; i++)
blob_write_bytes(blob, pipeline_obj->shaders[i]->hash, sizeof(pipeline_obj->shaders[i]->hash));
const size_t data_size = pipeline_obj->ps_epilog_binary_size + (pipeline_obj->num_stack_sizes * sizeof(uint32_t));
const size_t data_size = pipeline_obj->num_stack_sizes * sizeof(uint32_t);
blob_write_bytes(blob, pipeline_obj->data, data_size);
return true;
@ -390,22 +369,13 @@ radv_pipeline_cache_search(struct radv_device *device, struct vk_pipeline_cache
}
}
if (pipeline_obj->ps_epilog) {
struct radv_shader_part *ps_epilog = radv_shader_part_ref(pipeline_obj->ps_epilog);
if (pipeline->type == RADV_PIPELINE_GRAPHICS)
radv_pipeline_to_graphics(pipeline)->ps_epilog = ps_epilog;
else
radv_pipeline_to_graphics_lib(pipeline)->base.ps_epilog = ps_epilog;
}
pipeline->cache_object = object;
return true;
}
void
radv_pipeline_cache_insert(struct radv_device *device, struct vk_pipeline_cache *cache, struct radv_pipeline *pipeline,
struct radv_shader_part_binary *ps_epilog_binary, const unsigned char *sha1)
const unsigned char *sha1)
{
if (radv_is_cache_disabled(device))
return;
@ -419,10 +389,8 @@ radv_pipeline_cache_insert(struct radv_device *device, struct vk_pipeline_cache
num_shaders += pipeline->shaders[i] ? 1 : 0;
num_shaders += pipeline->gs_copy_shader ? 1 : 0;
unsigned ps_epilog_binary_size = ps_epilog_binary ? ps_epilog_binary->total_size : 0;
struct radv_pipeline_cache_object *pipeline_obj;
pipeline_obj = radv_pipeline_cache_object_create(&device->vk, num_shaders, sha1, 0, ps_epilog_binary_size);
pipeline_obj = radv_pipeline_cache_object_create(&device->vk, num_shaders, sha1, 0);
if (!pipeline_obj)
return;
@ -438,17 +406,6 @@ radv_pipeline_cache_insert(struct radv_device *device, struct vk_pipeline_cache
assert(idx == num_shaders);
if (ps_epilog_binary) {
memcpy(pipeline_obj->data, ps_epilog_binary, ps_epilog_binary_size);
struct radv_shader_part *ps_epilog;
if (pipeline->type == RADV_PIPELINE_GRAPHICS)
ps_epilog = radv_pipeline_to_graphics(pipeline)->ps_epilog;
else
ps_epilog = radv_pipeline_to_graphics_lib(pipeline)->base.ps_epilog;
pipeline_obj->ps_epilog = radv_shader_part_ref(ps_epilog);
}
/* Add the object to the cache */
pipeline->cache_object = vk_pipeline_cache_add_object(cache, &pipeline_obj->base);
}
@ -533,7 +490,7 @@ radv_ray_tracing_pipeline_cache_insert(struct radv_device *device, struct vk_pip
num_shaders += radv_ray_tracing_stage_is_compiled(&pipeline->stages[i]) ? 1 : 0;
struct radv_pipeline_cache_object *pipeline_obj =
radv_pipeline_cache_object_create(&device->vk, num_shaders, sha1, pipeline->stage_count, 0);
radv_pipeline_cache_object_create(&device->vk, num_shaders, sha1, pipeline->stage_count);
unsigned idx = 0;
if (pipeline->base.base.shaders[MESA_SHADER_INTERSECTION])

2
src/amd/vulkan/radv_pipeline_compute.c
View file

@ -230,7 +230,7 @@ radv_compute_pipeline_compile(struct radv_compute_pipeline *pipeline, struct rad
cs_stage.feedback.duration += os_time_get_nano() - stage_start;
if (!keep_executable_info) {
radv_pipeline_cache_insert(device, cache, &pipeline->base, NULL, hash);
radv_pipeline_cache_insert(device, cache, &pipeline->base, hash);
}
free(cs_binary);

75
src/amd/vulkan/radv_pipeline_graphics.c
View file

@ -261,8 +261,8 @@ radv_format_meta_fs_key(struct radv_device *device, VkFormat format)
}
static bool
radv_pipeline_needs_dynamic_ps_epilog(const struct radv_graphics_pipeline *pipeline,
VkGraphicsPipelineLibraryFlagBitsEXT lib_flags)
radv_pipeline_needs_ps_epilog(const struct radv_graphics_pipeline *pipeline,
VkGraphicsPipelineLibraryFlagBitsEXT lib_flags)
{
/* Use a PS epilog when the fragment shader is compiled without the fragment output interface. */
if ((pipeline->active_stages & VK_SHADER_STAGE_FRAGMENT_BIT) &&
@ -286,15 +286,11 @@ radv_pipeline_init_blend_state(struct radv_graphics_pipeline *pipeline, const st
struct radv_blend_state blend = {0};
unsigned spi_shader_col_format = 0;
if (radv_pipeline_needs_dynamic_ps_epilog(pipeline, lib_flags))
if (radv_pipeline_needs_ps_epilog(pipeline, lib_flags))
return blend;
if (ps) {
if (ps->info.has_epilog) {
spi_shader_col_format = pipeline->ps_epilog->spi_shader_col_format;
} else {
spi_shader_col_format = ps->info.ps.spi_shader_col_format;
}
spi_shader_col_format = ps->info.ps.spi_shader_col_format;
}
blend.cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
@ -796,12 +792,6 @@ radv_graphics_pipeline_import_lib(const struct radv_device *device, struct radv_
assert(!pipeline->base.gs_copy_shader);
pipeline->base.gs_copy_shader = radv_shader_ref(lib->base.base.gs_copy_shader);
}
/* Import the PS epilog if present. */
if (lib->base.ps_epilog) {
assert(!pipeline->ps_epilog);
pipeline->ps_epilog = radv_shader_part_ref(lib->base.ps_epilog);
}
}
/* Import the pipeline layout. */
@ -1931,17 +1921,8 @@ radv_generate_graphics_pipeline_key(const struct radv_device *device, const stru
if (device->primitives_generated_query)
key.primitives_generated_query = true;
if (radv_pipeline_needs_dynamic_ps_epilog(pipeline, lib_flags))
key.ps.dynamic_ps_epilog = true;
/* The fragment shader needs an epilog when both:
* - it's compiled without the fragment output interface with GPL
* - it's compiled on-demand because some dynamic states are enabled
*/
key.ps.has_epilog = (pipeline->active_stages & VK_SHADER_STAGE_FRAGMENT_BIT) &&
(((lib_flags & VK_GRAPHICS_PIPELINE_LIBRARY_FRAGMENT_SHADER_BIT_EXT) &&
!(lib_flags & VK_GRAPHICS_PIPELINE_LIBRARY_FRAGMENT_OUTPUT_INTERFACE_BIT_EXT)) ||
key.ps.dynamic_ps_epilog);
if (radv_pipeline_needs_ps_epilog(pipeline, lib_flags))
key.ps.has_epilog = true;
/* Disable MRT compaction when it's not possible to know both the written color outputs and the
* color blend attachments.
@ -2395,36 +2376,6 @@ radv_pipeline_load_retained_shaders(const struct radv_device *device, struct rad
}
}
static bool
radv_pipeline_create_ps_epilog(struct radv_device *device, struct radv_graphics_pipeline *pipeline,
const struct radv_pipeline_key *pipeline_key,
VkGraphicsPipelineLibraryFlagBitsEXT lib_flags,
struct radv_shader_part_binary **ps_epilog_binary)
{
bool needs_ps_epilog = false;
/* Do not compile a PS epilog as part of the pipeline when it needs to be dynamic. */
if (pipeline_key->ps.dynamic_ps_epilog)
return true;
if (pipeline->base.type == RADV_PIPELINE_GRAPHICS) {
needs_ps_epilog = pipeline->base.shaders[MESA_SHADER_FRAGMENT] &&
pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.has_epilog && !pipeline->ps_epilog;
} else {
assert(pipeline->base.type == RADV_PIPELINE_GRAPHICS_LIB);
needs_ps_epilog = (lib_flags & VK_GRAPHICS_PIPELINE_LIBRARY_FRAGMENT_OUTPUT_INTERFACE_BIT_EXT) &&
!(lib_flags & VK_GRAPHICS_PIPELINE_LIBRARY_FRAGMENT_SHADER_BIT_EXT);
}
if (needs_ps_epilog) {
pipeline->ps_epilog = radv_create_ps_epilog(device, &pipeline_key->ps.epilog, ps_epilog_binary);
if (!pipeline->ps_epilog)
return false;
}
return true;
}
static unsigned
radv_get_rasterization_prim(const struct radv_shader_stage *stages, const struct radv_pipeline_key *pipeline_key)
{
@ -2460,11 +2411,6 @@ radv_skip_graphics_pipeline_compile(const struct radv_device *device, const stru
if (!fast_linking_enabled)
return false;
/* Do not skip when the PS epilog needs to be compiled. */
if (!radv_pipeline_needs_dynamic_ps_epilog(pipeline, lib_flags) && pipeline->base.shaders[MESA_SHADER_FRAGMENT] &&
pipeline->base.shaders[MESA_SHADER_FRAGMENT]->info.has_epilog && !pipeline->ps_epilog)
return false;
/* Determine which shader stages have been imported. */
if (pipeline->base.shaders[MESA_SHADER_MESH]) {
binary_stages |= VK_SHADER_STAGE_MESH_BIT_EXT;
@ -2666,7 +2612,6 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk
{
struct radv_shader_binary *binaries[MESA_VULKAN_SHADER_STAGES] = {NULL};
struct radv_shader_binary *gs_copy_binary = NULL;
struct radv_shader_part_binary *ps_epilog_binary = NULL;
unsigned char hash[20];
bool keep_executable_info = radv_pipeline_capture_shaders(device, pipeline->base.create_flags);
bool keep_statistic_info = radv_pipeline_capture_shader_stats(device, pipeline->base.create_flags);
@ -2767,15 +2712,11 @@ radv_graphics_pipeline_compile(struct radv_graphics_pipeline *pipeline, const Vk
pipeline->base.is_internal, retained_shaders, noop_fs, pipeline->base.shaders,
binaries, &pipeline->base.gs_copy_shader, &gs_copy_binary);
if (!radv_pipeline_create_ps_epilog(device, pipeline, pipeline_key, lib_flags, &ps_epilog_binary))
return VK_ERROR_OUT_OF_DEVICE_MEMORY;
if (!skip_shaders_cache) {
radv_pipeline_cache_insert(device, cache, &pipeline->base, ps_epilog_binary, hash);
radv_pipeline_cache_insert(device, cache, &pipeline->base, hash);
}
free(gs_copy_binary);
free(ps_epilog_binary);
for (int i = 0; i < MESA_VULKAN_SHADER_STAGES; ++i) {
free(binaries[i]);
if (stages[i].nir) {
@ -4106,8 +4047,6 @@ radv_destroy_graphics_pipeline(struct radv_device *device, struct radv_graphics_
if (pipeline->base.gs_copy_shader)
radv_shader_unref(device, pipeline->base.gs_copy_shader);
if (pipeline->ps_epilog)
radv_shader_part_unref(device, pipeline->ps_epilog);
vk_free(&device->vk.alloc, pipeline->state_data);
}

7
src/amd/vulkan/radv_private.h
View file

@ -439,8 +439,7 @@ bool radv_pipeline_cache_search(struct radv_device *device, struct vk_pipeline_c
bool *found_in_application_cache);
void radv_pipeline_cache_insert(struct radv_device *device, struct vk_pipeline_cache *cache,
struct radv_pipeline *pipeline, struct radv_shader_part_binary *ps_epilog_binary,
const unsigned char *sha1);
struct radv_pipeline *pipeline, const unsigned char *sha1);
struct radv_ray_tracing_pipeline;
bool radv_ray_tracing_pipeline_cache_search(struct radv_device *device, struct vk_pipeline_cache *cache,
@ -1648,7 +1647,6 @@ struct radv_cmd_state {
VkShaderStageFlags active_stages;
struct radv_shader *shaders[MESA_VULKAN_SHADER_STAGES];
struct radv_shader *gs_copy_shader;
struct radv_shader_part *ps_epilog;
struct radv_shader *last_vgt_shader;
struct radv_shader *rt_prolog;
@ -2337,9 +2335,6 @@ struct radv_graphics_pipeline {
/* For vk_graphics_pipeline_state */
void *state_data;
/* Not NULL if graphics pipeline uses a PS epilog. */
struct radv_shader_part *ps_epilog;
/* Custom blend mode for internal operations. */
unsigned custom_blend_mode;

1
src/amd/vulkan/radv_shader.h
View file

@ -135,7 +135,6 @@ struct radv_pipeline_key {
/* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */
bool alpha_to_coverage_via_mrtz;
bool dynamic_ps_epilog;
bool has_epilog;
bool line_smooth_enabled;