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Author SHA1 Message Date
Georg Lehmann
1fe4d799e7 spirv: use nan/inf preserve for glsl.std.450 min/max instead of exact 
Foz-DB Navi48:
Totals from 135 (0.16% of 82405) affected shaders:
Instrs: 546831 -> 546552 (-0.05%); split: -0.05%, +0.00%
CodeSize: 3038664 -> 3037392 (-0.04%); split: -0.05%, +0.00%
Latency: 4360757 -> 4357294 (-0.08%); split: -0.08%, +0.00%
InvThroughput: 753593 -> 752997 (-0.08%)
Copies: 57180 -> 57207 (+0.05%)
VALU: 300705 -> 300513 (-0.06%)
SALU: 71339 -> 71364 (+0.04%)
VOPD: 30002 -> 29999 (-0.01%)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39641>
 2026-02-10 18:42:02 +00:00
Georg Lehmann
7c5a5755e2 spirv: use nan/inf preserve instead of exact for fp compare 
Foz-DB Navi48:
Totals from 438 (0.53% of 82405) affected shaders:
MaxWaves: 13164 -> 13076 (-0.67%)
Instrs: 259008 -> 257978 (-0.40%); split: -0.82%, +0.42%
CodeSize: 1415756 -> 1416404 (+0.05%); split: -0.22%, +0.27%
VGPRs: 21732 -> 21852 (+0.55%); split: -0.11%, +0.66%
Latency: 911833 -> 916968 (+0.56%); split: -0.20%, +0.76%
InvThroughput: 149739 -> 148995 (-0.50%); split: -0.99%, +0.49%
VClause: 4512 -> 4517 (+0.11%); split: -0.04%, +0.16%
SClause: 5429 -> 5452 (+0.42%); split: -0.31%, +0.74%
Copies: 11953 -> 11995 (+0.35%); split: -0.51%, +0.86%
PreSGPRs: 16326 -> 16321 (-0.03%); split: -0.04%, +0.01%
PreVGPRs: 14929 -> 14930 (+0.01%); split: -0.45%, +0.46%
VALU: 158092 -> 156926 (-0.74%); split: -1.31%, +0.57%
SALU: 25711 -> 25559 (-0.59%); split: -0.82%, +0.23%
VOPD: 76 -> 74 (-2.63%)

The regressions are in d3d9 shaders where fmulz is no longer reassociated,
because it now has the nan/inf preserve flags. This will be fixed later in the series.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39641>
 2026-02-10 18:42:02 +00:00
Karol Herbst
faf3a93e8f vtn: set default fp_math_ctrl values for kernels 
The kernel capabilty has the `FPFastMathMode` decoration, but not the
`FPFastMathDefault` execution mode, so a SPIR-V module not using
`SPV_KHR_float_controls2` has no way of setting any defaults.

Fixes: 9da2d21804 ("vtn: implement default fp_math_ctrl without using execution mode")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Tested-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39790>
 2026-02-10 15:14:57 +00:00
Karol Herbst
af954427bf vtn/opencl: flush denorms for cbrt() 
libclc doesn't so we have to. fixes math_brutefore cbrt on Iris.

Co-authored-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39794>
 2026-02-10 13:24:53 +00:00
Daniel Schürmann
e362011cca nir/loop_analyze: also set force_unroll if the array_size is larger than max_trip_count
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Loop peeling can reduce the trip_count. It is also not
necessary that the array_size exactly matches the trip_count.

Totals from 54 (0.06% of 84383) affected shaders: (Navi48)

MaxWaves: 758 -> 884 (+16.62%)
Instrs: 284511 -> 343292 (+20.66%)
CodeSize: 1524940 -> 1837996 (+20.53%)
VGPRs: 5904 -> 5544 (-6.10%)
Scratch: 18432 -> 0 (-inf%)
Latency: 7317179 -> 7186789 (-1.78%); split: -1.80%, +0.02%
InvThroughput: 1646024 -> 1545357 (-6.12%); split: -6.19%, +0.08%
VClause: 5840 -> 6867 (+17.59%); split: -1.92%, +19.50%
SClause: 6959 -> 7935 (+14.03%)
Copies: 25516 -> 31310 (+22.71%); split: -4.87%, +27.58%
Branches: 9205 -> 10571 (+14.84%); split: -3.25%, +18.09%
PreSGPRs: 5586 -> 5394 (-3.44%); split: -3.67%, +0.23%
PreVGPRs: 5087 -> 4674 (-8.12%); split: -8.18%, +0.06%
VALU: 145243 -> 174719 (+20.29%)
SALU: 53128 -> 67594 (+27.23%); split: -0.00%, +27.23%
VMEM: 8911 -> 10221 (+14.70%); split: -1.41%, +16.11%
SMEM: 8519 -> 9509 (+11.62%)
VOPD: 419 -> 796 (+89.98%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39778>
 2026-02-10 09:24:23 +00:00
Daniel Schürmann
b5439c4fbf nir/opt_loop_unroll: Always unroll loops with a known trip-count of 0 
Loop peeling decrements the calculated trip count, which might
result in a known trip-count of 0 for single-iteration loops.
Thus, also unroll loops if max_trip_count == 0 and exact_trip_count_known.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39778>
 2026-02-10 09:24:23 +00:00
Faith Ekstrand
02bade5cfa nir/lower_bool_to_bit_size: Make smarter canonicalization choices 
Instead of blindly taking the first source, take the first source that
isn't a constant.  That way we won't accidentally expand things to
32-bit just because a constant came first.

Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39725>
 2026-02-09 18:16:40 +00:00
Faith Ekstrand
711b3358a8 nir/lower_bool_to_bit_size: Use the correct num_components for conversions 
There's a nice little comment here saying we use the same write mask (an
out of date term in NIR) and swizzle but we're no longer actually doing
that.  Depending on nir_builder magic, we may actually generate a scalar
when we really want a vector.  The fix is to use more builder helpers
and just eat the potential copy.

Fixes: 3180656bbc ("nir: don't use nir_build_alu() with incomplete sources")
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39725>
 2026-02-09 18:16:40 +00:00
Alyssa Rosenzweig
91550d0709 nir: disable fast-math for lowering conversions 
the lowerings for e.g. f2f16_rtp have carefully written sequences using
Infinity. nir_opt_algebraic will stomp right through this. `feq x, inf`
without an exact flag is basically always a bug. Disable fast math here.
Fixes OpenCL CTS test_half on Iris.

Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39740>
 2026-02-09 17:22:02 +00:00
Iago Toral Quiroga
f6a2d14008 nir/opt_vectorize_load_store: allow sizes unaligned with high offset for loads
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This was added specifically for vectorized stores, so allow for loads.

Without this, the pass will fail to vectorize 2 consecutive 16-bit loads
into a single 32-bit load.

Fixes: 2ed79f80ba ("nir/load_store_vectorize: Skip new bit-sizes that are unaligned with high_offset")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39713>
 2026-02-09 07:59:21 +00:00
Vinson Lee
85fd63068e compiler/clc: Fix const correctness in libclc_add_generic_variants 
Fix compiler error:

../src/compiler/clc/nir_load_libclc.c:266:13: error: initializing
'char *' with an expression of type 'const char *' discards qualifiers
[-Werror,-Wincompatible-pointer-types-discards-qualifiers]
  266 |       char *U3AS1 = strstr(func->name, "U3AS1");
      |             ^       ~~~~~~~~~~~~~~~~~~~~~~~~~~~

glibc now provides C23-style type-generic string functions. strstr
returns const char * when passed a const char * argument. Update U3AS1
declaration to const since it's only used for offset calculation.

Fixes: 4a08ee7ecf ("spirv/libclc: Add generic versions of arithmetic functions")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39761>
 2026-02-08 22:48:13 +00:00
Kenneth Graunke
beb4b78fe7 intel: Rename intel_msaa_flags to intel_fs_config 
This started out as dynamic configuration for MSAA related state, but
has since expanded to cover many dynamic fragment shader options.

We rename it to intel_fs_config, similar to intel_tess_config, to
better indicate its purpose.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39748>
 2026-02-06 20:51:43 -08:00
Daniel Schürmann
f71a38e9de nir/opt_load_store_vectorize: don't use shared2 vectorization across blocks
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Besides the undesireable combinations this can produce,
it would also require to update the last_entry in every
previous block.

Totals from 99 (0.12% of 84383) affected shaders: (Navi48)
Instrs: 288989 -> 289727 (+0.26%); split: -0.02%, +0.28%
CodeSize: 1542572 -> 1546616 (+0.26%); split: -0.02%, +0.28%
SpillSGPRs: 17 -> 16 (-5.88%)
Latency: 2104020 -> 2103286 (-0.03%); split: -0.17%, +0.13%
InvThroughput: 472380 -> 472265 (-0.02%); split: -0.08%, +0.05%
VClause: 9778 -> 9779 (+0.01%)
Copies: 24937 -> 25173 (+0.95%); split: -0.05%, +0.99%
Branches: 10124 -> 10156 (+0.32%); split: -0.01%, +0.33%
PreSGPRs: 6112 -> 6091 (-0.34%)
PreVGPRs: 4079 -> 4069 (-0.25%); split: -0.39%, +0.15%
VALU: 120208 -> 120421 (+0.18%); split: -0.03%, +0.21%
SALU: 56338 -> 56312 (-0.05%); split: -0.09%, +0.04%
VOPD: 34 -> 37 (+8.82%)

Fixes: 4ca7ee7bd7 ('nir/opt_load_store_vectorize: Allow to vectorize at most one entry of each type across blocks')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39733>
 2026-02-06 16:34:15 +00:00
Daniel Schürmann
5e86cfac8e nir/opt_load_store_vectorize: Vectorize speculatable instructions across blocks
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This should always be safe.

Totals from 446 (0.53% of 84383) affected shaders: (Navi48)
Instrs: 995942 -> 994416 (-0.15%); split: -0.17%, +0.02%
CodeSize: 5500372 -> 5489900 (-0.19%); split: -0.20%, +0.01%
SpillSGPRs: 197 -> 195 (-1.02%)
Latency: 14872922 -> 14851646 (-0.14%); split: -0.15%, +0.00%
InvThroughput: 2395050 -> 2391537 (-0.15%); split: -0.15%, +0.00%
VClause: 20207 -> 20195 (-0.06%); split: -0.07%, +0.01%
SClause: 27090 -> 26427 (-2.45%); split: -2.51%, +0.07%
Copies: 84182 -> 84228 (+0.05%); split: -0.08%, +0.13%
Branches: 22927 -> 22928 (+0.00%)
PreSGPRs: 27275 -> 27524 (+0.91%); split: -0.02%, +0.93%
PreVGPRs: 29116 -> 29131 (+0.05%)
VALU: 545565 -> 545549 (-0.00%); split: -0.01%, +0.00%
SALU: 124275 -> 124329 (+0.04%); split: -0.05%, +0.09%
VMEM: 39044 -> 39030 (-0.04%)
SMEM: 44052 -> 43205 (-1.92%)
VOPD: 32354 -> 32337 (-0.05%); split: +0.02%, -0.07%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39373>
 2026-02-06 10:16:50 +00:00
Daniel Schürmann
4ca7ee7bd7 nir/opt_load_store_vectorize: Allow to vectorize at most one entry of each type across blocks 
The idea is to initialize the vectorization table with one
entry from the previous blocks if it's the same for all predecessors.
In order to not speculatively load out-of-bounds, backends need to
set a new bounds_checked_modes option indicating variable modes
for which per-component bounds checks are supported.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39373>
 2026-02-06 10:16:50 +00:00
Daniel Schürmann
0a07ea20e6 nir/opt_load_store_vectorize: create add_entry_to_hash_table() helper 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39373>
 2026-02-06 10:16:50 +00:00
Daniel Schürmann
e5bd9cbf90 nir/opt_load_store_vectorize: use linear allocator instead of ralloc 
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39373>
 2026-02-06 10:16:49 +00:00
Georg Lehmann
5e2f28e723 nir: remove split unpack_half opcodes
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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39511>
 2026-02-06 06:12:36 +00:00
Georg Lehmann
81e3162cf8 microsoft/compiler: switch to a backend specific unpack half opcode 
Sadly, just f2f32 isn't enough for dxil.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39511>
 2026-02-06 06:12:36 +00:00
Georg Lehmann
45cb1d3b6f nir/opt_algebraic: remove unpack_half_2x16_split 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39511>
 2026-02-06 06:12:36 +00:00
Georg Lehmann
5a2ef27f7d nir/format_convert: use f2f32 instead of unpack_half 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39511>
 2026-02-06 06:12:36 +00:00
Georg Lehmann
a3bd2ae465 nir/opt_16bit_tex_image: remove unpack_half support 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39511>
 2026-02-06 06:12:36 +00:00
Georg Lehmann
6f7d4cd75b nir/lower_tex: use f2f32 instead of unpack_half 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39511>
 2026-02-06 06:12:36 +00:00
Georg Lehmann
609c46cf23 nir/lower_alu_width: emit f2f32 for unpack_half_2x16 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39511>
 2026-02-06 06:12:36 +00:00
Georg Lehmann
b18d9c1b33 nir/opt_algebraic: optimize unpack_32_2x16 of extract 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39511>
 2026-02-06 06:12:36 +00:00
Timothy Arceri
da6c3ad237 nir: speedup nir_find_inlinable_uniforms() 
Here we speedup nir_find_inlinable_uniforms() by making sure we only
check a src is inlinable once.

If we have a bunch of nested if-statements where the conditions keep
building on the alu chains of previous conditions we can end up
with exponential processing times due to repeatedly processing the
same srcs over and over.

A big cause of the exponential grow seems to be instructions like
`ffma %594, %594, %599` or `fmul %600, %600` where each essentially
causes us to process the entire previous part of the chain
twice.

Shaders such as that in issue #14663 took multiple minutes to
compile previously, calling collect_src_uniforms billions of times
and now compile within a second with this change.

Closes: mesa/mesa#14663

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39664>
 2026-02-05 23:19:29 +00:00
Timothy Arceri
aaea962808 nir: update asserts in inline uniforms 
collect_src_uniforms() is now only called internally and uni_offsets
should never be NULL.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39664>
 2026-02-05 23:19:29 +00:00
Timothy Arceri
0410377b63 nir: make nir_add_inlinable_uniforms() private 
Hasn't been used externally since e93592dc62

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39664>
 2026-02-05 23:19:28 +00:00
Timothy Arceri
257875034d nir: make nir_collect_src_uniforms() private 
Hasn't been used externally since e93592dc62

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39664>
 2026-02-05 23:19:28 +00:00
Caterina Shablia
1e6793f7b1 spirv: plumb spirv-dis --offsets 
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39554>
 2026-02-04 12:05:10 +00:00
Karol Herbst
e5bf1f5aff nir/opt_offsets: support nvidias intrinsics 
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39525>
 2026-02-03 22:23:51 +00:00
Karol Herbst
cb60e4d14f nir/opt_offsets: support negative offsets and 64 bit sources 
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39525>
 2026-02-03 22:23:51 +00:00
Karol Herbst
4add3959e9 nir: add BASE to nvidia memory intrinsics 
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39525>
 2026-02-03 22:23:50 +00:00
Karol Herbst
e779538ad2 nir: add nvidia IO intrinsics 
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39525>
 2026-02-03 22:23:50 +00:00
Marek Olšák
a3f022d0a2 nir: reassociate a $op (b ? #c : #d) for div, mod, rem
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This eliminates expensive div, mod, rem opcodes with non-constant src1 being
constant src1 hiding behind bcsel.

gcc and LLVM are missing this.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39560>
 2026-02-02 21:34:48 +00:00
Marek Olšák
30e9f0bdf3 nir/opt_16bit_tex_image: lower dst of load_buffer_amd 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39474>
 2026-02-02 17:56:52 +00:00
Marek Olšák
44bc1e6bf4 nir: add dest_type to load_buffer_amd 
for lowering the result to 16 bits

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39474>
 2026-02-02 17:56:52 +00:00
Marek Olšák
9eaaf9e525 nir: add ACCESS_SPARSE 
trying to reduce the combinatorial explosion of intrinsics

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39474>
 2026-02-02 17:56:52 +00:00
Marek Olšák
3350bca3eb nir/print: fix a crash due to unhandled GLSL_SAMPLER_DIM_EXTERNAL 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39474>
 2026-02-02 17:56:52 +00:00
Georg Lehmann
bdc084aae5 nir/algebraic: make subexpression inexact on creation
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Removes the runtime code for this, and means we propergate the
signed zero/inf/nan checks to subexpessions too, not just exact.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
 2026-01-31 15:30:25 +00:00
Georg Lehmann
293d2e3b0d nir/algebraic: remove ability to create Value from Expression 
Not used, and it would break in the future.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
 2026-01-31 15:30:25 +00:00
Georg Lehmann
ad6f8291bf nir/opt_algebraic: rework ignore_exact to work like other internal conditions 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
 2026-01-31 15:30:25 +00:00
Georg Lehmann
a879b9a5d5 nir/search: preserve nan/inf/sz if any alu in a replaced expression did 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
 2026-01-31 15:30:25 +00:00
Georg Lehmann
575affaf48 nir/search: gather union of all fp_math_ctrl 
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39616>
 2026-01-31 15:30:25 +00:00
Karol Herbst
dc03f94e07 clc: fix compile compatability with LLVM-22
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See d090311aa7

Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:26 +00:00
Karol Herbst
24d20df3d6 nir: fix nir_fixup_is_exported for LLVM-22 
Starting with LLVM-22 we won't see the kernel wrapper anymore, and this
is a trivial fix to get around this.

See: 5458eb2511

Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:25 +00:00
Karol Herbst
6eda573a8a clc: enable generic address space and seq_cst and device scope atomic features 
This is going to be required with LLVM-22.

See 423bdb2bf2

Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:25 +00:00
Karol Herbst
01e1392139 clc: support some atomic and generic address space features 
Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:25 +00:00
Karol Herbst
7f9a7ed553 clc: reorder headers to fix compilation errors due to UNUSED 
Cc: mesa-stable
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39374>
 2026-01-30 16:06:25 +00:00
Georg Lehmann
70f0e75262 nir/opt_algebraic: optimize pack_half_2x16_rtz of float converted from 16bit 
Foz-DB Navi48:
Totals from 177 (0.21% of 82405) affected shaders:
Instrs: 326628 -> 325955 (-0.21%); split: -0.21%, +0.00%
CodeSize: 1726720 -> 1722500 (-0.24%); split: -0.24%, +0.00%
Latency: 5076631 -> 5075700 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 596010 -> 595598 (-0.07%); split: -0.07%, +0.00%
VClause: 3613 -> 3616 (+0.08%)
Copies: 24427 -> 24501 (+0.30%); split: -0.06%, +0.36%
VALU: 182468 -> 182029 (-0.24%); split: -0.24%, +0.00%
SALU: 55449 -> 55452 (+0.01%); split: -0.01%, +0.01%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39531>
 2026-01-29 14:44:37 +00:00