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intel: Rename intel_msaa_flags to intel_fs_config

Browse source 
This started out as dynamic configuration for MSAA related state, but
has since expanded to cover many dynamic fragment shader options.

We rename it to intel_fs_config, similar to intel_tess_config, to
better indicate its purpose.

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39748>
This commit is contained in:
Kenneth Graunke 2026-02-06 14:57:15 -08:00
parent 9aa93039d9
commit beb4b78fe7
35 changed files with 201 additions and 201 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/compiler/nir/nir_divergence_analysis.c
View file

@ -347,7 +347,7 @@ visit_intrinsic(nir_intrinsic_instr *instr, struct divergence_state *state)
case nir_intrinsic_load_descriptor_set_agx:
case nir_intrinsic_load_sm_count_nv:
case nir_intrinsic_load_warps_per_sm_nv:
case nir_intrinsic_load_fs_msaa_intel:
case nir_intrinsic_load_fs_config_intel:
case nir_intrinsic_load_constant_base_ptr:
case nir_intrinsic_load_const_buf_base_addr_lvp:
case nir_intrinsic_load_max_polygon_intel:

4
src/compiler/nir/nir_intrinsics.py
View file

@ -2643,8 +2643,8 @@ load("push_data_intel", [1], [BASE, RANGE, ACCESS], [CAN_ELIMINATE, CAN_REORDER]
# Dynamic tesselation parameters (see intel_tess_config).
system_value("tess_config_intel", 1)
# Dynamic fragment shader parameters (see intel_msaa_flags) .
system_value("fs_msaa_intel", 1)
# Dynamic fragment shader parameters (see intel_fs_config) .
system_value("fs_config_intel", 1)
# Per primitive remapping table offset.
system_value("per_primitive_remap_intel", 1)

2
src/gallium/drivers/crocus/crocus_state.c
View file

@ -6461,7 +6461,7 @@ crocus_upload_dirty_render_state(struct crocus_context *ice,
intel_set_ps_dispatch_state(&ps, &batch->screen->devinfo,
wm_prog_data,
ice->state.framebuffer.samples,
0 /* msaa_flags */);
0 /* fs_config */);
ps.DispatchGRFStartRegisterForConstantSetupData0 =
elk_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);

4
src/gallium/drivers/iris/iris_context.h
View file

@ -308,7 +308,7 @@ struct iris_fs_data {
uint64_t inputs;
unsigned num_varying_inputs;
unsigned msaa_flags_param;
unsigned fs_config_param;
uint32_t flat_inputs;
uint8_t computed_depth_mode;
@ -1358,7 +1358,7 @@ iris_cs_push_const_total_size(const struct iris_compiled_shader *shader,
unsigned threads);
uint32_t
iris_fs_barycentric_modes(const struct iris_compiled_shader *shader,
enum intel_msaa_flags pushed_msaa_flags);
enum intel_fs_config pushed_fs_config);
bool iris_use_tcs_multi_patch(struct iris_screen *screen);
bool iris_indirect_ubos_use_sampler(struct iris_screen *screen);
const struct nir_shader_compiler_options *

2
src/gallium/drivers/iris/iris_indirect_gen.c
View file

@ -293,7 +293,7 @@ emit_indirect_generate_draw(struct iris_batch *batch,
#endif
intel_set_ps_dispatch_state(&ps, devinfo, wm_prog_data,
1 /* rasterization_samples */,
0 /* msaa_flags */);
0 /* fs_config */);
ps.VectorMaskEnable = fs_data->uses_vmask;

10
src/gallium/drivers/iris/iris_program.c
View file

@ -84,7 +84,7 @@ iris_apply_brw_wm_prog_data(struct iris_compiled_shader *shader,
iris->urb_setup_attribs_count = brw->urb_setup_attribs_count;
iris->num_varying_inputs = brw->num_varying_inputs;
iris->msaa_flags_param = brw->msaa_flags_param;
iris->fs_config_param = brw->fs_config_param;
iris->flat_inputs = brw->flat_inputs;
iris->inputs = brw->inputs;
iris->computed_depth_mode = brw->computed_depth_mode;
@ -296,7 +296,7 @@ iris_apply_elk_wm_prog_data(struct iris_compiled_shader *shader,
iris->urb_setup_attribs_count = elk->urb_setup_attribs_count;
iris->num_varying_inputs = elk->num_varying_inputs;
iris->msaa_flags_param = elk->msaa_flags_param;
iris->fs_config_param = elk->fs_config_param;
iris->flat_inputs = elk->flat_inputs;
iris->inputs = elk->inputs;
iris->computed_depth_mode = elk->computed_depth_mode;
@ -4031,16 +4031,16 @@ iris_cs_push_const_total_size(const struct iris_compiled_shader *shader,
uint32_t
iris_fs_barycentric_modes(const struct iris_compiled_shader *shader,
enum intel_msaa_flags pushed_msaa_flags)
enum intel_fs_config pushed_fs_config)
{
if (shader->brw_prog_data) {
return wm_prog_data_barycentric_modes(brw_wm_prog_data(shader->brw_prog_data),
pushed_msaa_flags);
pushed_fs_config);
} else {
#ifdef INTEL_USE_ELK
assert(shader->elk_prog_data);
return elk_wm_prog_data_barycentric_modes(elk_wm_prog_data(shader->elk_prog_data),
pushed_msaa_flags);
pushed_fs_config);
#else
UNREACHABLE("no elk support");
#endif

2
src/gallium/drivers/iris/iris_state.c
View file

@ -7525,7 +7525,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
#endif
intel_set_ps_dispatch_state(&ps, batch->screen->devinfo,
wm_prog_data, util_framebuffer_get_num_samples(cso_fb),
0 /* msaa_flags */);
0 /* fs_config */);
#if GFX_VER == 12
assert(fs_data->dispatch_multi == 0 ||

2
src/intel/blorp/blorp_genX_exec_brw.h
View file

@ -891,7 +891,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
intel_set_ps_dispatch_state(&ps, devinfo, prog_data,
params->num_samples,
0 /* msaa_flags */);
0 /* fs_config */);
ps.DispatchGRFStartRegisterForConstantSetupData0 =
brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);

4
src/intel/blorp/blorp_genX_exec_elk.h
View file

@ -937,7 +937,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
if (prog_data) {
intel_set_ps_dispatch_state(&ps, devinfo, prog_data,
params->num_samples,
0 /* msaa_flags */);
0 /* fs_config */);
ps.DispatchGRFStartRegisterForConstantSetupData0 =
elk_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);
@ -1017,7 +1017,7 @@ blorp_emit_ps_config(struct blorp_batch *batch,
if (prog_data) {
intel_set_ps_dispatch_state(&ps, devinfo, prog_data,
params->num_samples,
0 /* msaa_flags */);
0 /* fs_config */);
ps.DispatchGRFStartRegisterForConstantSetupData0 =
elk_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);

4
src/intel/common/intel_genX_state_brw.h
View file

@ -44,7 +44,7 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
const struct intel_device_info *devinfo,
const struct brw_wm_prog_data *prog_data,
unsigned rasterization_samples,
enum intel_msaa_flags msaa_flags)
enum intel_fs_config fs_config)
{
assert(rasterization_samples != 0);
@ -88,7 +88,7 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
#endif
const bool is_persample_dispatch =
brw_wm_prog_data_is_persample(prog_data, msaa_flags);
brw_wm_prog_data_is_persample(prog_data, fs_config);
if (is_persample_dispatch) {
/* TGL PRMs, Volume 2d: Command Reference: Structures:

4
src/intel/common/intel_genX_state_elk.h
View file

@ -48,7 +48,7 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
const struct intel_device_info *devinfo,
const struct elk_wm_prog_data *prog_data,
unsigned rasterization_samples,
enum intel_msaa_flags msaa_flags)
enum intel_fs_config fs_config)
{
assert(rasterization_samples != 0);
@ -73,7 +73,7 @@ intel_set_ps_dispatch_state(struct GENX(3DSTATE_PS) *ps,
#endif
const bool is_persample_dispatch =
elk_wm_prog_data_is_persample(prog_data, msaa_flags);
elk_wm_prog_data_is_persample(prog_data, fs_config);
if (is_persample_dispatch) {
/* Starting with SandyBridge (where we first get MSAA), the different

6
src/intel/compiler/brw/brw_builder.cpp
View file

@ -244,12 +244,12 @@ brw_fetch_barycentric_reg(const brw_builder &bld, uint8_t regs[2])
}
void
brw_check_dynamic_msaa_flag(const brw_builder &bld,
brw_check_dynamic_fs_config(const brw_builder &bld,
const struct brw_wm_prog_data *wm_prog_data,
enum intel_msaa_flags flag)
enum intel_fs_config flag)
{
brw_inst *inst = bld.AND(bld.null_reg_ud(),
brw_dynamic_msaa_flags(wm_prog_data),
brw_dynamic_fs_config(wm_prog_data),
brw_imm_ud(flag));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
}

4
src/intel/compiler/brw/brw_builder.h
View file

@ -1106,9 +1106,9 @@ brw_reg
brw_fetch_barycentric_reg(const brw_builder &bld, uint8_t regs[2]);
void
brw_check_dynamic_msaa_flag(const brw_builder &bld,
brw_check_dynamic_fs_config(const brw_builder &bld,
const struct brw_wm_prog_data *wm_prog_data,
enum intel_msaa_flags flag);
enum intel_fs_config flag);
inline brw_inst *
brw_transform_inst(const brw_builder &bld, brw_inst *inst,

30
src/intel/compiler/brw/brw_compile_fs.cpp
View file

@ -202,8 +202,8 @@ brw_emit_interpolation_setup(brw_shader &s)
ubld.MOV(cps_size, brw_imm_ud(0x00000101));
break;
case INTEL_SOMETIMES:
brw_check_dynamic_msaa_flag(ubld, wm_prog_data,
INTEL_MSAA_FLAG_COARSE_RT_WRITES);
brw_check_dynamic_fs_config(ubld, wm_prog_data,
INTEL_FS_CONFIG_COARSE_RT_WRITES);
set_predicate_inv(BRW_PREDICATE_NORMAL, false,
ubld.MOV(cps_size, r1_0));
@ -335,8 +335,8 @@ brw_emit_interpolation_setup(brw_shader &s)
const brw_builder dbld =
abld.exec_all().group(MIN2(16, s.dispatch_width) * 2, 0);
brw_check_dynamic_msaa_flag(dbld, wm_prog_data,
INTEL_MSAA_FLAG_COARSE_RT_WRITES);
brw_check_dynamic_fs_config(dbld, wm_prog_data,
INTEL_FS_CONFIG_COARSE_RT_WRITES);
int_pixel_offset_x = dbld.vgrf(BRW_TYPE_UW);
set_predicate(BRW_PREDICATE_NORMAL,
@ -514,8 +514,8 @@ brw_emit_interpolation_setup(brw_shader &s)
assert(barys[0] && sample_barys[0]);
if (!loaded_flag) {
brw_check_dynamic_msaa_flag(ubld, wm_prog_data,
INTEL_MSAA_FLAG_PERSAMPLE_INTERP);
brw_check_dynamic_fs_config(ubld, wm_prog_data,
INTEL_FS_CONFIG_PERSAMPLE_INTERP);
}
for (unsigned j = 0; j < s.dispatch_width / 8; j++) {
@ -1524,23 +1524,23 @@ brw_compile_fs(const struct brw_compiler *compiler,
uint32_t f = 0;
if (key->multisample_fbo == INTEL_ALWAYS)
f |= INTEL_MSAA_FLAG_MULTISAMPLE_FBO;
f |= INTEL_FS_CONFIG_MULTISAMPLE_FBO;
if (key->alpha_to_coverage == INTEL_ALWAYS)
f |= INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE;
f |= INTEL_FS_CONFIG_ALPHA_TO_COVERAGE;
if (key->provoking_vertex_last == INTEL_ALWAYS)
f |= INTEL_MSAA_FLAG_PROVOKING_VERTEX_LAST;
f |= INTEL_FS_CONFIG_PROVOKING_VERTEX_LAST;
if (key->persample_interp == INTEL_ALWAYS) {
f |= INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH |
INTEL_MSAA_FLAG_PERSAMPLE_INTERP;
f |= INTEL_FS_CONFIG_PERSAMPLE_DISPATCH |
INTEL_FS_CONFIG_PERSAMPLE_INTERP;
}
if (prog_data->coarse_pixel_dispatch == INTEL_ALWAYS)
f |= INTEL_MSAA_FLAG_COARSE_RT_WRITES;
f |= INTEL_FS_CONFIG_COARSE_RT_WRITES;
BRW_NIR_PASS(nir_inline_sysval, nir_intrinsic_load_fs_msaa_intel, f);
BRW_NIR_PASS(nir_inline_sysval, nir_intrinsic_load_fs_config_intel, f);
}
brw_postprocess_nir_opts(pt, key->base.robust_flags);
@ -1997,13 +1997,13 @@ brw_compute_sbe_per_vertex_urb_read(const struct intel_vue_map *prev_stage_vue_m
~((1u << last_slot) - 1);
*out_flat_inputs |= remapped_flat_inputs;
last_slot = prev_stage_vue_map->num_slots - 1;
*out_primitive_id_offset = INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_MESH;
*out_primitive_id_offset = INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_MESH;
num_varyings = prev_stage_vue_map->num_slots - first_slot;
} else if (mesh) {
/* When using Mesh, the PrimitiveID is in the per-primitive block. */
if (wm_prog_data->urb_setup[VARYING_SLOT_PRIMITIVE_ID] >= 0)
num_varyings--;
*out_primitive_id_offset = INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_MESH;
*out_primitive_id_offset = INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_MESH;
} else if (inputs_read & VARYING_BIT_PRIMITIVE_ID) {
int primitive_id_slot;
if (prev_stage_vue_map->varying_to_slot[VARYING_SLOT_PRIMITIVE_ID] < 0) {

16
src/intel/compiler/brw/brw_compiler.h
View file

@ -731,10 +731,10 @@ struct brw_wm_prog_data {
enum intel_sometimes provoking_vertex_last;
/**
* Push constant location of intel_msaa_flags (dynamic configuration of the
* Push constant location of intel_fs_config (dynamic configuration of the
* pixel shader) in bytes.
*/
unsigned msaa_flags_param;
unsigned fs_config_param;
/**
* Push constant location of the remapping offset in the instruction heap
@ -905,28 +905,28 @@ _brw_wm_prog_data_dispatch_grf_start_reg(const struct brw_wm_prog_data *prog_dat
static inline bool
brw_wm_prog_data_is_persample(const struct brw_wm_prog_data *prog_data,
enum intel_msaa_flags pushed_msaa_flags)
enum intel_fs_config pushed_fs_config)
{
return intel_fs_is_persample(prog_data->persample_dispatch,
prog_data->sample_shading,
pushed_msaa_flags);
pushed_fs_config);
}
static inline uint32_t
wm_prog_data_barycentric_modes(const struct brw_wm_prog_data *prog_data,
enum intel_msaa_flags pushed_msaa_flags)
enum intel_fs_config pushed_fs_config)
{
return intel_fs_barycentric_modes(prog_data->persample_dispatch,
prog_data->barycentric_interp_modes,
pushed_msaa_flags);
pushed_fs_config);
}
static inline bool
brw_wm_prog_data_is_coarse(const struct brw_wm_prog_data *prog_data,
enum intel_msaa_flags pushed_msaa_flags)
enum intel_fs_config pushed_fs_config)
{
return intel_fs_is_coarse(prog_data->coarse_pixel_dispatch,
pushed_msaa_flags);
pushed_fs_config);
}
struct brw_push_const_block {

24
src/intel/compiler/brw/brw_from_nir.cpp
View file

@ -3448,8 +3448,8 @@ emit_samplepos_setup(nir_to_brw_state &ntb)
}
if (wm_prog_data->persample_dispatch == INTEL_SOMETIMES) {
brw_check_dynamic_msaa_flag(abld, wm_prog_data,
INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH);
brw_check_dynamic_fs_config(abld, wm_prog_data,
INTEL_FS_CONFIG_PERSAMPLE_DISPATCH);
for (unsigned i = 0; i < 2; i++) {
set_predicate(BRW_PREDICATE_NORMAL,
bld.SEL(offset(pos, abld, i), offset(pos, abld, i),
@ -3522,8 +3522,8 @@ emit_sampleid_setup(nir_to_brw_state &ntb)
abld.AND(sample_id, tmp, brw_imm_w(0xf));
if (key->multisample_fbo == INTEL_SOMETIMES) {
brw_check_dynamic_msaa_flag(abld, wm_prog_data,
INTEL_MSAA_FLAG_MULTISAMPLE_FBO);
brw_check_dynamic_fs_config(abld, wm_prog_data,
INTEL_FS_CONFIG_MULTISAMPLE_FBO);
set_predicate(BRW_PREDICATE_NORMAL,
abld.SEL(sample_id, sample_id, brw_imm_ud(0)));
}
@ -3575,8 +3575,8 @@ emit_samplemaskin_setup(nir_to_brw_state &ntb)
if (wm_prog_data->persample_dispatch == INTEL_ALWAYS)
return mask;
brw_check_dynamic_msaa_flag(abld, wm_prog_data,
INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH);
brw_check_dynamic_fs_config(abld, wm_prog_data,
INTEL_FS_CONFIG_PERSAMPLE_DISPATCH);
set_predicate(BRW_PREDICATE_NORMAL, abld.SEL(mask, mask, coverage_mask));
return mask;
@ -3620,8 +3620,8 @@ emit_shading_rate_setup(nir_to_brw_state &ntb)
if (wm_prog_data->coarse_pixel_dispatch == INTEL_ALWAYS)
return rate;
brw_check_dynamic_msaa_flag(abld, wm_prog_data,
INTEL_MSAA_FLAG_COARSE_RT_WRITES);
brw_check_dynamic_fs_config(abld, wm_prog_data,
INTEL_FS_CONFIG_COARSE_RT_WRITES);
set_predicate(BRW_PREDICATE_NORMAL, abld.SEL(rate, rate, brw_imm_ud(0)));
return rate;
@ -4039,9 +4039,9 @@ brw_from_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
if (wm_prog_key->multisample_fbo == INTEL_SOMETIMES) {
struct brw_wm_prog_data *wm_prog_data = brw_wm_prog_data(s.prog_data);
brw_check_dynamic_msaa_flag(bld.exec_all().group(8, 0),
brw_check_dynamic_fs_config(bld.exec_all().group(8, 0),
wm_prog_data,
INTEL_MSAA_FLAG_MULTISAMPLE_FBO);
INTEL_FS_CONFIG_MULTISAMPLE_FBO);
flag_reg = brw_flag_reg(0, 0);
}
@ -4129,9 +4129,9 @@ brw_from_nir_emit_fs_intrinsic(nir_to_brw_state &ntb,
break;
}
case nir_intrinsic_load_fs_msaa_intel:
case nir_intrinsic_load_fs_config_intel:
bld.MOV(retype(dest, BRW_TYPE_UD),
brw_dynamic_msaa_flags(brw_wm_prog_data(s.prog_data)));
brw_dynamic_fs_config(brw_wm_prog_data(s.prog_data)));
break;
case nir_intrinsic_load_max_polygon_intel:

14
src/intel/compiler/brw/brw_lower_logical_sends.cpp
View file

@ -441,8 +441,8 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_fb_write_inst *write,
const brw_builder &ubld =
bld.scalar_group().annotate("Coarse bit");
brw_reg coarse_bit =
ubld.AND(brw_dynamic_msaa_flags(prog_data),
brw_imm_ud(INTEL_MSAA_FLAG_COARSE_RT_WRITES));
ubld.AND(brw_dynamic_fs_config(prog_data),
brw_imm_ud(INTEL_FS_CONFIG_COARSE_RT_WRITES));
desc_reg = component(coarse_bit, 0);
}
} else {
@ -485,8 +485,8 @@ lower_fb_write_logical_send(const brw_builder &bld, brw_fb_write_inst *write,
send->has_side_effects = true;
if (double_rt_writes) {
brw_check_dynamic_msaa_flag(bld, prog_data,
INTEL_MSAA_FLAG_COARSE_RT_WRITES);
brw_check_dynamic_fs_config(bld, prog_data,
INTEL_FS_CONFIG_COARSE_RT_WRITES);
bld.IF(BRW_PREDICATE_NORMAL);
{
brw_send_inst *coarse_inst = brw_clone_inst(*bld.shader, send)->as_send();
@ -1875,12 +1875,12 @@ lower_interpolator_logical_send(const brw_builder &bld, brw_inst *inst,
if (wm_prog_data->coarse_pixel_dispatch == INTEL_ALWAYS) {
desc_imm |= (1 << 15);
} else if (wm_prog_data->coarse_pixel_dispatch == INTEL_SOMETIMES) {
STATIC_ASSERT(INTEL_MSAA_FLAG_COARSE_PI_MSG == (1 << 15));
STATIC_ASSERT(INTEL_FS_CONFIG_COARSE_PI_MSG == (1 << 15));
brw_reg orig_desc = desc;
const brw_builder &ubld = bld.exec_all().group(8, 0);
desc = ubld.vgrf(BRW_TYPE_UD);
ubld.AND(desc, brw_dynamic_msaa_flags(wm_prog_data),
brw_imm_ud(INTEL_MSAA_FLAG_COARSE_PI_MSG));
ubld.AND(desc, brw_dynamic_fs_config(wm_prog_data),
brw_imm_ud(INTEL_FS_CONFIG_COARSE_PI_MSG));
/* And, if it's AT_OFFSET, we might have a non-trivial descriptor */
if (orig_desc.file == IMM) {

10
src/intel/compiler/brw/brw_nir.c
View file

@ -1334,22 +1334,22 @@ brw_nir_lower_fs_inputs(nir_shader *nir,
nir_shader_get_entrypoint(nir)))), *b = &_b;
nir_def *index = nir_ubitfield_extract_imm(
b,
nir_load_fs_msaa_intel(b),
INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_OFFSET,
INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_SIZE);
nir_load_fs_config_intel(b),
INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_OFFSET,
INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_SIZE);
nir_def *per_vertex_offset =
nir_iadd_imm(
b,
brw_nir_vertex_attribute_offset(
b, nir_imul_imm(b, index, 4), devinfo),
devinfo->grf_size);
/* When the attribute index is INTEL_MSAA_FLAG_PRIMITIVE_ID_MESH_INDEX,
/* When the attribute index is INTEL_FS_CONFIG_PRIMITIVE_ID_MESH_INDEX,
* it means the value is coming from the per-primitive block. We always
* lay out PrimitiveID at offset 0 in the per-primitive block.
*/
nir_def *attribute_offset = nir_bcsel(
b,
nir_ieq_imm(b, index, INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_MESH),
nir_ieq_imm(b, index, INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_MESH),
nir_imm_int(b, 0), per_vertex_offset);
indirect_primitive_id =
nir_load_attribute_payload_intel(b, 1, 32, attribute_offset);

4
src/intel/compiler/brw/brw_nir_lower_alpha_to_coverage.c
View file

@ -151,9 +151,9 @@ brw_nir_lower_alpha_to_coverage(nir_shader *shader)
nir_def *dither_mask = build_dither_mask(&b, color0);
dither_mask = nir_iand(&b, sample_mask, dither_mask);
nir_def *msaa_flags = nir_load_fs_msaa_intel(&b);
nir_def *fs_config = nir_load_fs_config_intel(&b);
nir_def *alpha_to_coverage =
nir_test_mask(&b, msaa_flags, INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE);
nir_test_mask(&b, fs_config, INTEL_FS_CONFIG_ALPHA_TO_COVERAGE);
dither_mask = nir_bcsel(&b, alpha_to_coverage,
dither_mask, sample_mask_write->src[0].ssa);

4
src/intel/compiler/brw/brw_nir_lower_fs_barycentrics.c
View file

@ -45,9 +45,9 @@ lower_flat_inputs(nir_builder *b, nir_intrinsic_instr *intrin, void *data)
nir_def *first_vtx = load_input_vertex(b, intrin, 0, intrin->def.num_components);
nir_def *last_vtx = load_input_vertex(b, intrin, 2, intrin->def.num_components);
nir_def *msaa_flags = nir_load_fs_msaa_intel(b);
nir_def *fs_config = nir_load_fs_config_intel(b);
nir_def *last = nir_test_mask(b, msaa_flags, INTEL_MSAA_FLAG_PROVOKING_VERTEX_LAST);
nir_def *last = nir_test_mask(b, fs_config, INTEL_FS_CONFIG_PROVOKING_VERTEX_LAST);
nir_def *input_vertex = nir_bcsel(b, last, last_vtx, first_vtx);
nir_def_replace(&intrin->def, input_vertex);

10
src/intel/compiler/brw/brw_nir_wa_18019110168.c
View file

@ -558,16 +558,16 @@ brw_nir_frag_convert_attrs_prim_to_vert_indirect(struct nir_shader *nir,
per_primitive_stride = align(per_primitive_stride, devinfo->grf_size);
nir_def *msaa_flags = nir_load_fs_msaa_intel(b);
nir_def *fs_config = nir_load_fs_config_intel(b);
nir_def *needs_remapping = nir_test_mask(
b, msaa_flags, INTEL_MSAA_FLAG_PER_PRIMITIVE_REMAPPING);
b, fs_config, INTEL_FS_CONFIG_PER_PRIMITIVE_REMAPPING);
nir_push_if(b, needs_remapping);
{
nir_def *first_slot =
nir_ubitfield_extract_imm(
b, msaa_flags,
INTEL_MSAA_FLAG_FIRST_VUE_SLOT_OFFSET,
INTEL_MSAA_FLAG_FIRST_VUE_SLOT_SIZE);
b, fs_config,
INTEL_FS_CONFIG_FIRST_VUE_SLOT_OFFSET,
INTEL_FS_CONFIG_FIRST_VUE_SLOT_SIZE);
nir_def *remap_table_addr =
nir_pack_64_2x32_split(
b,

6
src/intel/compiler/brw/brw_shader.h
View file

@ -270,12 +270,12 @@ sample_mask_flag_subreg(const brw_shader &s)
}
inline brw_reg
brw_dynamic_msaa_flags(const struct brw_wm_prog_data *wm_prog_data)
brw_dynamic_fs_config(const struct brw_wm_prog_data *wm_prog_data)
{
return byte_offset(
brw_uniform_reg(
wm_prog_data->msaa_flags_param / REG_SIZE, BRW_TYPE_UD),
wm_prog_data->msaa_flags_param % REG_SIZE);
wm_prog_data->fs_config_param / REG_SIZE, BRW_TYPE_UD),
wm_prog_data->fs_config_param % REG_SIZE);
}
inline brw_reg

22
src/intel/compiler/elk/elk_compiler.h
View file

@ -799,7 +799,7 @@ struct elk_wm_prog_data {
*/
enum elk_sometimes alpha_to_coverage;
unsigned msaa_flags_param;
unsigned fs_config_param;
/**
* Mask of which interpolation modes are required by the fragment shader.
@ -938,21 +938,21 @@ _elk_wm_prog_data_reg_blocks(const struct elk_wm_prog_data *prog_data,
static inline bool
elk_wm_prog_data_is_persample(const struct elk_wm_prog_data *prog_data,
enum intel_msaa_flags pushed_msaa_flags)
enum intel_fs_config pushed_fs_config)
{
if (pushed_msaa_flags & INTEL_MSAA_FLAG_ENABLE_DYNAMIC) {
if (!(pushed_msaa_flags & INTEL_MSAA_FLAG_MULTISAMPLE_FBO))
if (pushed_fs_config & INTEL_FS_CONFIG_ENABLE_DYNAMIC) {
if (!(pushed_fs_config & INTEL_FS_CONFIG_MULTISAMPLE_FBO))
return false;
if (prog_data->sample_shading)
assert(pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH);
assert(pushed_fs_config & INTEL_FS_CONFIG_PERSAMPLE_DISPATCH);
if (pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH)
if (pushed_fs_config & INTEL_FS_CONFIG_PERSAMPLE_DISPATCH)
assert(prog_data->persample_dispatch != ELK_NEVER);
else
assert(prog_data->persample_dispatch != ELK_ALWAYS);
return (pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH) != 0;
return (pushed_fs_config & INTEL_FS_CONFIG_PERSAMPLE_DISPATCH) != 0;
}
assert(prog_data->persample_dispatch == ELK_ALWAYS ||
@ -963,19 +963,19 @@ elk_wm_prog_data_is_persample(const struct elk_wm_prog_data *prog_data,
static inline uint32_t
elk_wm_prog_data_barycentric_modes(const struct elk_wm_prog_data *prog_data,
enum intel_msaa_flags pushed_msaa_flags)
enum intel_fs_config pushed_fs_config)
{
uint32_t modes = prog_data->barycentric_interp_modes;
/* In the non dynamic case, we can just return the computed modes from
* compilation time.
*/
if (!(pushed_msaa_flags & INTEL_MSAA_FLAG_ENABLE_DYNAMIC))
if (!(pushed_fs_config & INTEL_FS_CONFIG_ENABLE_DYNAMIC))
return modes;
if (pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_INTERP) {
if (pushed_fs_config & INTEL_FS_CONFIG_PERSAMPLE_INTERP) {
assert(prog_data->persample_dispatch == ELK_ALWAYS ||
(pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH));
(pushed_fs_config & INTEL_FS_CONFIG_PERSAMPLE_DISPATCH));
/* Making dynamic per-sample interpolation work is a bit tricky. The
* hardware will hang if SAMPLE is requested but per-sample dispatch is

6
src/intel/compiler/elk/elk_fs.cpp
View file

@ -7250,12 +7250,12 @@ namespace elk {
}
void
check_dynamic_msaa_flag(const fs_builder &bld,
check_dynamic_fs_config(const fs_builder &bld,
const struct elk_wm_prog_data *wm_prog_data,
enum intel_msaa_flags flag)
enum intel_fs_config flag)
{
elk_fs_inst *inst = bld.AND(bld.null_reg_ud(),
dynamic_msaa_flags(wm_prog_data),
dynamic_fs_config(wm_prog_data),
elk_imm_ud(flag));
inst->conditional_mod = ELK_CONDITIONAL_NZ;
}

8
src/intel/compiler/elk/elk_fs.h
View file

@ -517,16 +517,16 @@ namespace elk {
fetch_barycentric_reg(const elk::fs_builder &bld, uint8_t regs[2]);
inline elk_fs_reg
dynamic_msaa_flags(const struct elk_wm_prog_data *wm_prog_data)
dynamic_fs_config(const struct elk_wm_prog_data *wm_prog_data)
{
return elk_fs_reg(UNIFORM, wm_prog_data->msaa_flags_param,
return elk_fs_reg(UNIFORM, wm_prog_data->fs_config_param,
ELK_REGISTER_TYPE_UD);
}
void
check_dynamic_msaa_flag(const fs_builder &bld,
check_dynamic_fs_config(const fs_builder &bld,
const struct elk_wm_prog_data *wm_prog_data,
enum intel_msaa_flags flag);
enum intel_fs_config flag);
bool
lower_src_modifiers(elk_fs_visitor *v, elk_bblock_t *block, elk_fs_inst *inst, unsigned i);

16
src/intel/compiler/elk/elk_fs_nir.cpp
View file

@ -3387,8 +3387,8 @@ emit_samplepos_setup(nir_to_elk_state &ntb)
}
if (wm_prog_data->persample_dispatch == ELK_SOMETIMES) {
check_dynamic_msaa_flag(abld, wm_prog_data,
INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH);
check_dynamic_fs_config(abld, wm_prog_data,
INTEL_FS_CONFIG_PERSAMPLE_DISPATCH);
for (unsigned i = 0; i < 2; i++) {
set_predicate(ELK_PREDICATE_NORMAL,
bld.SEL(offset(pos, abld, i), offset(pos, abld, i),
@ -3508,8 +3508,8 @@ emit_sampleid_setup(nir_to_elk_state &ntb)
}
if (key->multisample_fbo == ELK_SOMETIMES) {
check_dynamic_msaa_flag(abld, wm_prog_data,
INTEL_MSAA_FLAG_MULTISAMPLE_FBO);
check_dynamic_fs_config(abld, wm_prog_data,
INTEL_FS_CONFIG_MULTISAMPLE_FBO);
set_predicate(ELK_PREDICATE_NORMAL,
abld.SEL(sample_id, sample_id, elk_imm_ud(0)));
}
@ -3559,8 +3559,8 @@ emit_samplemaskin_setup(nir_to_elk_state &ntb)
if (wm_prog_data->persample_dispatch == ELK_ALWAYS)
return mask;
check_dynamic_msaa_flag(abld, wm_prog_data,
INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH);
check_dynamic_fs_config(abld, wm_prog_data,
INTEL_FS_CONFIG_PERSAMPLE_DISPATCH);
set_predicate(ELK_PREDICATE_NORMAL, abld.SEL(mask, mask, coverage_mask));
return mask;
@ -3835,9 +3835,9 @@ fs_nir_emit_fs_intrinsic(nir_to_elk_state &ntb,
if (wm_prog_key->multisample_fbo == ELK_SOMETIMES) {
struct elk_wm_prog_data *wm_prog_data = elk_wm_prog_data(s.prog_data);
check_dynamic_msaa_flag(bld.exec_all().group(8, 0),
check_dynamic_fs_config(bld.exec_all().group(8, 0),
wm_prog_data,
INTEL_MSAA_FLAG_MULTISAMPLE_FBO);
INTEL_FS_CONFIG_MULTISAMPLE_FBO);
flag_reg = elk_flag_reg(0, 0);
}

4
src/intel/compiler/elk/elk_fs_visitor.cpp
View file

@ -285,8 +285,8 @@ elk_fs_visitor::emit_interpolation_setup_gfx6()
assert(barys[0] && sample_barys[0]);
if (!loaded_flag) {
check_dynamic_msaa_flag(ubld, wm_prog_data,
INTEL_MSAA_FLAG_PERSAMPLE_INTERP);
check_dynamic_fs_config(ubld, wm_prog_data,
INTEL_FS_CONFIG_PERSAMPLE_INTERP);
}
for (unsigned j = 0; j < dispatch_width / 8; j++) {

4
src/intel/compiler/elk/elk_nir_lower_alpha_to_coverage.c
View file

@ -156,9 +156,9 @@ elk_nir_lower_alpha_to_coverage(nir_shader *shader,
if (key->alpha_to_coverage == ELK_SOMETIMES) {
nir_def *push_flags =
nir_load_uniform(&b, 1, 32, nir_imm_int(&b, prog_data->msaa_flags_param * 4));
nir_load_uniform(&b, 1, 32, nir_imm_int(&b, prog_data->fs_config_param * 4));
nir_def *alpha_to_coverage =
nir_test_mask(&b, push_flags, INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE);
nir_test_mask(&b, push_flags, INTEL_FS_CONFIG_ALPHA_TO_COVERAGE);
dither_mask = nir_bcsel(&b, alpha_to_coverage,
dither_mask, sample_mask_write->src[0].ssa);
}

102
src/intel/compiler/intel_shader_enums.h
View file

@ -81,57 +81,57 @@ enum intel_tess_configs {
INTEL_TESS_CONFIG_ISOLINES = BITFIELD_BIT(31)
};
#define INTEL_MSAA_FLAG_FIRST_VUE_SLOT_OFFSET (19)
#define INTEL_MSAA_FLAG_FIRST_VUE_SLOT_SIZE (6)
#define INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_OFFSET (25)
#define INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_SIZE (6)
#define INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_MESH (32)
#define INTEL_FS_CONFIG_FIRST_VUE_SLOT_OFFSET (19)
#define INTEL_FS_CONFIG_FIRST_VUE_SLOT_SIZE (6)
#define INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_OFFSET (25)
#define INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_SIZE (6)
#define INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_MESH (32)
enum intel_msaa_flags {
enum intel_fs_config {
/** Must be set whenever any dynamic MSAA is used
*
* This flag mostly exists to let us assert that the driver understands
* dynamic MSAA so we don't run into trouble with drivers that don't.
*/
INTEL_MSAA_FLAG_ENABLE_DYNAMIC = (1 << 0),
INTEL_FS_CONFIG_ENABLE_DYNAMIC = (1 << 0),
/** True if the framebuffer is multisampled */
INTEL_MSAA_FLAG_MULTISAMPLE_FBO = (1 << 1),
INTEL_FS_CONFIG_MULTISAMPLE_FBO = (1 << 1),
/** True if this shader has been dispatched per-sample */
INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH = (1 << 2),
INTEL_FS_CONFIG_PERSAMPLE_DISPATCH = (1 << 2),
/** True if inputs should be interpolated per-sample by default */
INTEL_MSAA_FLAG_PERSAMPLE_INTERP = (1 << 3),
INTEL_FS_CONFIG_PERSAMPLE_INTERP = (1 << 3),
/** True if this shader has been dispatched with alpha-to-coverage */
INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE = (1 << 4),
INTEL_FS_CONFIG_ALPHA_TO_COVERAGE = (1 << 4),
/** True if provoking vertex is last */
INTEL_MSAA_FLAG_PROVOKING_VERTEX_LAST = (1 << 5),
INTEL_FS_CONFIG_PROVOKING_VERTEX_LAST = (1 << 5),
/** True if we need to apply Wa_18019110168 remapping */
INTEL_MSAA_FLAG_PER_PRIMITIVE_REMAPPING = (1 << 6),
INTEL_FS_CONFIG_PER_PRIMITIVE_REMAPPING = (1 << 6),
/** True if this shader has been dispatched coarse
*
* This is intentionally chose to be bit 15 to correspond to the coarse bit
* in the pixel interpolator messages.
*/
INTEL_MSAA_FLAG_COARSE_PI_MSG = (1 << 15),
INTEL_FS_CONFIG_COARSE_PI_MSG = (1 << 15),
/** True if this shader has been dispatched coarse
*
* This is intentionally chose to be bit 18 to correspond to the coarse bit
* in the render target messages.
*/
INTEL_MSAA_FLAG_COARSE_RT_WRITES = (1 << 18),
INTEL_FS_CONFIG_COARSE_RT_WRITES = (1 << 18),
/** First slot read in the VUE
*
* This is not a flag but a value that cover 6bits.
*/
INTEL_MSAA_FLAG_FIRST_VUE_SLOT = (1 << INTEL_MSAA_FLAG_FIRST_VUE_SLOT_OFFSET),
INTEL_FS_CONFIG_FIRST_VUE_SLOT = (1 << INTEL_FS_CONFIG_FIRST_VUE_SLOT_OFFSET),
/** Index of the PrimitiveID attribute relative to the first read
* attribute.
@ -140,9 +140,9 @@ enum intel_msaa_flags {
* PrimitiveID is coming from the PerPrimitive block, written by the Mesh
* shader.
*/
INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX = (1 << INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_OFFSET),
INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX = (1 << INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_OFFSET),
};
MESA_DEFINE_CPP_ENUM_BITFIELD_OPERATORS(intel_msaa_flags)
MESA_DEFINE_CPP_ENUM_BITFIELD_OPERATORS(intel_fs_config)
/**
* @defgroup Tessellator parameter enumerations.
@ -403,26 +403,26 @@ intel_tess_config(uint32_t input_vertices,
static inline bool
intel_fs_is_persample(enum intel_sometimes shader_persample_dispatch,
bool shader_per_sample_shading,
enum intel_msaa_flags pushed_msaa_flags)
enum intel_fs_config pushed_fs_config)
{
if (shader_persample_dispatch != INTEL_SOMETIMES)
return shader_persample_dispatch;
assert(pushed_msaa_flags & INTEL_MSAA_FLAG_ENABLE_DYNAMIC);
assert(pushed_fs_config & INTEL_FS_CONFIG_ENABLE_DYNAMIC);
if (!(pushed_msaa_flags & INTEL_MSAA_FLAG_MULTISAMPLE_FBO))
if (!(pushed_fs_config & INTEL_FS_CONFIG_MULTISAMPLE_FBO))
return false;
if (shader_per_sample_shading)
assert(pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH);
assert(pushed_fs_config & INTEL_FS_CONFIG_PERSAMPLE_DISPATCH);
return (pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH) != 0;
return (pushed_fs_config & INTEL_FS_CONFIG_PERSAMPLE_DISPATCH) != 0;
}
static inline uint32_t
intel_fs_barycentric_modes(enum intel_sometimes shader_persample_dispatch,
uint32_t shader_barycentric_modes,
enum intel_msaa_flags pushed_msaa_flags)
enum intel_fs_config pushed_fs_config)
{
/* In the non dynamic case, we can just return the computed shader_barycentric_modes from
* compilation time.
@ -432,10 +432,10 @@ intel_fs_barycentric_modes(enum intel_sometimes shader_persample_dispatch,
uint32_t modes = shader_barycentric_modes;
assert(pushed_msaa_flags & INTEL_MSAA_FLAG_ENABLE_DYNAMIC);
assert(pushed_fs_config & INTEL_FS_CONFIG_ENABLE_DYNAMIC);
if (pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_INTERP) {
assert(pushed_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH);
if (pushed_fs_config & INTEL_FS_CONFIG_PERSAMPLE_INTERP) {
assert(pushed_fs_config & INTEL_FS_CONFIG_PERSAMPLE_DISPATCH);
/* Making dynamic per-sample interpolation work is a bit tricky. The
* hardware will hang if SAMPLE is requested but per-sample dispatch is
@ -516,18 +516,18 @@ intel_fs_barycentric_modes(enum intel_sometimes shader_persample_dispatch,
static inline bool
intel_fs_is_coarse(enum intel_sometimes shader_coarse_pixel_dispatch,
enum intel_msaa_flags pushed_msaa_flags)
enum intel_fs_config pushed_fs_config)
{
if (shader_coarse_pixel_dispatch != INTEL_SOMETIMES)
return shader_coarse_pixel_dispatch;
assert(pushed_msaa_flags & INTEL_MSAA_FLAG_ENABLE_DYNAMIC);
assert(pushed_fs_config & INTEL_FS_CONFIG_ENABLE_DYNAMIC);
assert((pushed_msaa_flags & INTEL_MSAA_FLAG_COARSE_RT_WRITES) ?
assert((pushed_fs_config & INTEL_FS_CONFIG_COARSE_RT_WRITES) ?
shader_coarse_pixel_dispatch != INTEL_NEVER :
shader_coarse_pixel_dispatch != INTEL_ALWAYS);
return (pushed_msaa_flags & INTEL_MSAA_FLAG_COARSE_RT_WRITES) != 0;
return (pushed_fs_config & INTEL_FS_CONFIG_COARSE_RT_WRITES) != 0;
}
struct intel_fs_params {
@ -543,50 +543,50 @@ struct intel_fs_params {
bool per_primitive_remapping;
};
static inline enum intel_msaa_flags
intel_fs_msaa_flags(struct intel_fs_params params)
static inline enum intel_fs_config
intel_fs_config(struct intel_fs_params params)
{
enum intel_msaa_flags fs_msaa_flags = INTEL_MSAA_FLAG_ENABLE_DYNAMIC;
enum intel_fs_config fs_config = INTEL_FS_CONFIG_ENABLE_DYNAMIC;
if (params.rasterization_samples > 1) {
fs_msaa_flags |= INTEL_MSAA_FLAG_MULTISAMPLE_FBO;
fs_config |= INTEL_FS_CONFIG_MULTISAMPLE_FBO;
if (params.shader_sample_shading)
fs_msaa_flags |= INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH;
fs_config |= INTEL_FS_CONFIG_PERSAMPLE_DISPATCH;
if (params.shader_sample_shading ||
(params.state_sample_shading &&
(params.shader_min_sample_shading *
params.rasterization_samples) > 1)) {
fs_msaa_flags |= INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH |
INTEL_MSAA_FLAG_PERSAMPLE_INTERP;
fs_config |= INTEL_FS_CONFIG_PERSAMPLE_DISPATCH |
INTEL_FS_CONFIG_PERSAMPLE_INTERP;
}
}
if (!(fs_msaa_flags & INTEL_MSAA_FLAG_PERSAMPLE_DISPATCH) &&
if (!(fs_config & INTEL_FS_CONFIG_PERSAMPLE_DISPATCH) &&
params.coarse_pixel) {
fs_msaa_flags |= INTEL_MSAA_FLAG_COARSE_PI_MSG |
INTEL_MSAA_FLAG_COARSE_RT_WRITES;
fs_config |= INTEL_FS_CONFIG_COARSE_PI_MSG |
INTEL_FS_CONFIG_COARSE_RT_WRITES;
}
if (params.alpha_to_coverage)
fs_msaa_flags |= INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE;
fs_config |= INTEL_FS_CONFIG_ALPHA_TO_COVERAGE;
assert(params.first_vue_slot < (1 << INTEL_MSAA_FLAG_FIRST_VUE_SLOT_SIZE));
fs_msaa_flags |= (enum intel_msaa_flags)(
params.first_vue_slot << INTEL_MSAA_FLAG_FIRST_VUE_SLOT_OFFSET);
assert(params.first_vue_slot < (1 << INTEL_FS_CONFIG_FIRST_VUE_SLOT_SIZE));
fs_config |= (enum intel_fs_config)(
params.first_vue_slot << INTEL_FS_CONFIG_FIRST_VUE_SLOT_OFFSET);
assert(params.primitive_id_index < (1u << INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_SIZE));
fs_msaa_flags |= (enum intel_msaa_flags)(
params.primitive_id_index << INTEL_MSAA_FLAG_PRIMITIVE_ID_INDEX_OFFSET);
assert(params.primitive_id_index < (1u << INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_SIZE));
fs_config |= (enum intel_fs_config)(
params.primitive_id_index << INTEL_FS_CONFIG_PRIMITIVE_ID_INDEX_OFFSET);
if (params.provoking_vertex_last)
fs_msaa_flags |= INTEL_MSAA_FLAG_PROVOKING_VERTEX_LAST;
fs_config |= INTEL_FS_CONFIG_PROVOKING_VERTEX_LAST;
if (params.per_primitive_remapping)
fs_msaa_flags |= INTEL_MSAA_FLAG_PER_PRIMITIVE_REMAPPING;
fs_config |= INTEL_FS_CONFIG_PER_PRIMITIVE_REMAPPING;
return fs_msaa_flags;
return fs_config;
}
#define INTEL_MAX_EMBEDDED_SAMPLERS (4096)

24
src/intel/vulkan/anv_nir_compute_push_layout.c
View file

@ -195,13 +195,13 @@ anv_nir_compute_push_layout(nir_shader *nir,
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
if (push_info->fragment_dynamic) {
const uint32_t fs_msaa_flags_start =
anv_drv_const_offset(gfx.fs_msaa_flags);
const uint32_t fs_msaa_flags_end =
fs_msaa_flags_start +
anv_drv_const_size(gfx.fs_msaa_flags);
push_start = MIN2(push_start, fs_msaa_flags_start);
push_end = MAX2(push_end, fs_msaa_flags_end);
const uint32_t fs_config_start =
anv_drv_const_offset(gfx.fs_config);
const uint32_t fs_config_end =
fs_config_start +
anv_drv_const_size(gfx.fs_config);
push_start = MIN2(push_start, fs_config_start);
push_end = MAX2(push_end, fs_config_end);
}
if (needs_wa_18019110168) {
@ -303,7 +303,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
* To solve that issue we push an additional dummy push constant buffer in
* legacy pipelines to align everything. The compiler then adds a SEL
* instruction to source the PrimitiveID from the right location based on a
* dynamic bit in fs_msaa_intel.
* dynamic bit in fs_config_intel.
*/
const bool needs_padding_per_primitive =
needs_wa_18019110168 ||
@ -433,10 +433,10 @@ anv_nir_compute_push_layout(nir_shader *nir,
container_of(prog_data, struct brw_wm_prog_data, base);
if (push_info->fragment_dynamic) {
const uint32_t fs_msaa_flags_offset =
anv_drv_const_offset(gfx.fs_msaa_flags);
assert(fs_msaa_flags_offset >= push_start);
wm_prog_data->msaa_flags_param = fs_msaa_flags_offset - push_start;
const uint32_t fs_config_offset =
anv_drv_const_offset(gfx.fs_config);
assert(fs_config_offset >= push_start);
wm_prog_data->fs_config_param = fs_config_offset - push_start;
}
if (needs_wa_18019110168) {
const uint32_t fs_per_prim_remap_offset =

8
src/intel/vulkan/anv_private.h
View file

@ -1988,7 +1988,7 @@ enum anv_gfx_state_bits {
ANV_GFX_STATE_WA_18038825448, /* Fake state to implement workaround */
ANV_GFX_STATE_WA_14024997852, /* Fake state to implement workaround */
ANV_GFX_STATE_TBIMR_TILE_PASS_INFO,
ANV_GFX_STATE_FS_MSAA_FLAGS,
ANV_GFX_STATE_FS_CONFIG,
ANV_GFX_STATE_TESS_CONFIG,
ANV_GFX_STATE_MESH_PROVOKING_VERTEX,
@ -2383,10 +2383,10 @@ struct anv_gfx_dynamic_state {
/**
* Dynamic msaa flags, this value can be different from
* anv_push_constants::gfx::fs_msaa_flags, as the push constant value only
* anv_push_constants::gfx::fs_config, as the push constant value only
* needs to be updated for fragment shaders dynamically checking the value.
*/
enum intel_msaa_flags fs_msaa_flags;
enum intel_fs_config fs_config;
/**
* Dynamic tesselation configuration (see enum intel_tess_config).
@ -4286,7 +4286,7 @@ struct anv_push_constants {
union {
struct {
/** Dynamic MSAA value */
uint32_t fs_msaa_flags;
uint32_t fs_config;
/** Dynamic TCS/TES configuration */
uint32_t tess_config;

2
src/intel/vulkan/anv_util.c
View file

@ -206,7 +206,7 @@ anv_gfx_state_bit_to_str(enum anv_gfx_state_bits state)
NAME(WA_18019816803);
NAME(WA_14018283232);
NAME(TBIMR_TILE_PASS_INFO);
NAME(FS_MSAA_FLAGS);
NAME(FS_CONFIG);
NAME(TESS_CONFIG);
NAME(MESH_PROVOKING_VERTEX);
default: UNREACHABLE("invalid state");

34
src/intel/vulkan/genX_gfx_state.c
View file

@ -841,9 +841,9 @@ update_urb_config(struct anv_gfx_dynamic_state *hw_state,
}
ALWAYS_INLINE static void
update_fs_msaa_flags(struct anv_gfx_dynamic_state *hw_state,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_cmd_graphics_state *gfx)
update_fs_config(struct anv_gfx_dynamic_state *hw_state,
const struct vk_dynamic_graphics_state *dyn,
const struct anv_cmd_graphics_state *gfx)
{
const struct brw_wm_prog_data *wm_prog_data = get_gfx_wm_prog_data(gfx);
@ -858,8 +858,8 @@ update_fs_msaa_flags(struct anv_gfx_dynamic_state *hw_state,
const struct brw_mesh_prog_data *mesh_prog_data = get_gfx_mesh_prog_data(gfx);
enum intel_msaa_flags fs_msaa_flags =
intel_fs_msaa_flags((struct intel_fs_params) {
enum intel_fs_config fs_config =
intel_fs_config((struct intel_fs_params) {
.shader_sample_shading = wm_prog_data->sample_shading,
.shader_min_sample_shading = wm_prog_data->min_sample_shading,
.state_sample_shading = wm_prog_data->api_sample_shading,
@ -873,7 +873,7 @@ update_fs_msaa_flags(struct anv_gfx_dynamic_state *hw_state,
mesh_prog_data->map.wa_18019110168_active,
});
SET(FS_MSAA_FLAGS, fs_msaa_flags, fs_msaa_flags);
SET(FS_CONFIG, fs_config, fs_config);
}
static bool
@ -1023,7 +1023,7 @@ update_ps(struct anv_gfx_dynamic_state *hw_state,
struct GENX(3DSTATE_PS) ps = {};
intel_set_ps_dispatch_state(&ps, device->info, wm_prog_data,
MAX2(dyn->ms.rasterization_samples, 1),
hw_state->fs_msaa_flags);
hw_state->fs_config);
SET(PS, ps.KernelStartPointer0,
fs->kernel.offset +
@ -1062,7 +1062,7 @@ update_ps(struct anv_gfx_dynamic_state *hw_state,
SET(PS, ps.PositionXYOffsetSelect,
!wm_prog_data->uses_pos_offset ? POSOFFSET_NONE :
brw_wm_prog_data_is_persample(wm_prog_data,
hw_state->fs_msaa_flags) ?
hw_state->fs_config) ?
POSOFFSET_SAMPLE : POSOFFSET_CENTROID);
}
@ -1076,7 +1076,7 @@ update_ps_extra_wm(struct anv_gfx_dynamic_state *hw_state,
return;
UNUSED const bool uses_coarse_pixel =
brw_wm_prog_data_is_coarse(wm_prog_data, hw_state->fs_msaa_flags);
brw_wm_prog_data_is_coarse(wm_prog_data, hw_state->fs_config);
uint32_t InputCoverageMaskState = ICMS_NONE;
assert(!wm_prog_data->inner_coverage); /* Not available in SPIR-V */
@ -1091,7 +1091,7 @@ update_ps_extra_wm(struct anv_gfx_dynamic_state *hw_state,
SET(PS_EXTRA, ps_extra.PixelShaderIsPerSample,
brw_wm_prog_data_is_persample(wm_prog_data,
hw_state->fs_msaa_flags));
hw_state->fs_config));
#if GFX_VER >= 11
SET(PS_EXTRA, ps_extra.PixelShaderIsPerCoarsePixel, uses_coarse_pixel);
#endif
@ -1103,7 +1103,7 @@ update_ps_extra_wm(struct anv_gfx_dynamic_state *hw_state,
#endif
SET(WM, wm.BarycentricInterpolationMode,
wm_prog_data_barycentric_modes(wm_prog_data, hw_state->fs_msaa_flags));
wm_prog_data_barycentric_modes(wm_prog_data, hw_state->fs_config));
#if INTEL_WA_18038825448_GFX_VER
SET(WA_18038825448, coarse_state, uses_coarse_pixel ?
@ -2306,7 +2306,7 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
assert(gfx->shaders[gfx->streamout_stage] != NULL);
assert(gfx->instance_multiplier != 0);
/* Do this before update_fs_msaa_flags() for primitive_id_index */
/* Do this before update_fs_config() for primitive_id_index */
if (gfx->dirty & ANV_CMD_DIRTY_ALL_SHADERS(device))
update_sbe(hw_state, gfx, device);
@ -2315,7 +2315,7 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_RS_PROVOKING_VERTEX) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_FSR))
update_fs_msaa_flags(hw_state, dyn, gfx);
update_fs_config(hw_state, dyn, gfx);
if (gfx->dirty & ANV_CMD_DIRTY_PRERASTER_SHADERS)
update_urb_config(hw_state, gfx, device);
@ -2326,7 +2326,7 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
#endif
if ((gfx->dirty & ANV_CMD_DIRTY_PS) ||
BITSET_TEST(hw_state->pack_dirty, ANV_GFX_STATE_FS_MSAA_FLAGS)) {
BITSET_TEST(hw_state->pack_dirty, ANV_GFX_STATE_FS_CONFIG)) {
update_ps(hw_state, device, dyn, gfx);
update_ps_extra_wm(hw_state, gfx);
}
@ -3659,8 +3659,8 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_MESH_BIT_EXT;
#endif
if (IS_DIRTY(FS_MSAA_FLAGS)) {
push_consts->gfx.fs_msaa_flags = hw_state->fs_msaa_flags;
if (IS_DIRTY(FS_CONFIG)) {
push_consts->gfx.fs_config = hw_state->fs_config;
const struct brw_mesh_prog_data *mesh_prog_data = get_gfx_mesh_prog_data(gfx);
if (mesh_prog_data) {
@ -4052,7 +4052,7 @@ genX(cmd_buffer_flush_gfx_hw_state)(struct anv_cmd_buffer *cmd_buffer)
if (wm_prog_data) {
genX(cmd_buffer_set_coarse_pixel_active)(
cmd_buffer,
brw_wm_prog_data_is_coarse(wm_prog_data, hw_state->fs_msaa_flags));
brw_wm_prog_data_is_coarse(wm_prog_data, hw_state->fs_config));
}
#endif

2
src/intel/vulkan/genX_simple_shader.c
View file

@ -199,7 +199,7 @@ genX(emit_simpler_shader_init_fragment)(struct anv_simple_shader *state)
anv_batch_emit(batch, GENX(3DSTATE_PS), ps) {
intel_set_ps_dispatch_state(&ps, device->info, prog_data,
1 /* rasterization_samples */,
0 /* msaa_flags */);
0 /* fs_config */);
ps.VectorMaskEnable = prog_data->uses_vmask;

2
src/intel/vulkan_hasvk/genX_pipeline.c
View file

@ -1692,7 +1692,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS), ps) {
intel_set_ps_dispatch_state(&ps, devinfo, wm_prog_data,
ms != NULL ? ms->rasterization_samples : 1,
0 /* msaa_flags */);
0 /* fs_config */);
ps.KernelStartPointer0 = fs_bin->kernel.offset +
elk_wm_prog_data_prog_offset(wm_prog_data, ps, 0);