Commit graph

141701 commits

Author SHA1 Message Date
Marek Olšák
3cde2f96f9 radeonsi: use ac_build_bit_count instead of opencoding it
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
2021-06-20 01:22:01 -04:00
Marek Olšák
70b5a5cbbf radeonsi: fix compile failures with SI_PRIM_DISCARD_DEBUG enabled
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11486>
2021-06-20 01:22:01 -04:00
Eleni Maria Stea
b4d90b1182 egl: fix in expected type
Function mincore expects a pointer of type char* but we use an unsigned
char* instead generating signedness related warnings.

v2: Made the fix FreeBSD specific because the type is unsigned char* for
Linux and char* for FreeBSD. (Adam Jackson)

v3: We'd rather cast the param to (void*) to avoid warnings in all
systems (Adam Jackson)

Signed-off-by: Eleni Maria Stea <elene.mst@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11298>
2021-06-19 19:34:20 +00:00
Jason Ekstrand
7b8199e4a2 crocus: Drop extra_aux support
This exists for combined MCS+CCS or HiZ+CCS which was introduced on
Tigerlake.  Crocus will never support hardware that has these features
so there's no point carrying the dead copied+pasted code from iris.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11483>
2021-06-19 14:57:25 +00:00
Bas Nieuwenhuizen
82de184c3a radv: Enable VK_KHR_acceleration_structure with RADV_PERFTEST=rt.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Bas Nieuwenhuizen
c27e3a6248 radv: Add rt perftest flag.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Bas Nieuwenhuizen
438cb7f9a3 radv: Expose formats for acceleration structure.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Bas Nieuwenhuizen
9920eadf83 radv: Implement load_vulkan_descriptor for acceleration structures.
It always uses nir_address_format_64bit_global.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Bas Nieuwenhuizen
85e39cb325 radv: Convert lower_intrinsics to a switch statement
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Bas Nieuwenhuizen
a4b3ce5d56 radv: Add acceleration structure descriptor set support.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Bas Nieuwenhuizen
0dad88b469 radv: Implement device-side BVH building.
Same naive algorithm as the host build.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Bas Nieuwenhuizen
d51a4b4c4b radv: Add initial CPU BVH building.
The algorithm used for the BVH:

1) first create 1 leaf per primitive (triangle/aabb/instance)
2) Then create internal layers from the bottom up until we are left with
   1 node in the top layer. Node i in the layer will have children
   (i*4+0) ... (i*4+3) in the previous layer.

This results in a very naive algorithm but it is also very simple to implement.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Bas Nieuwenhuizen
67e949a8f8 radv: Use the global BO list for acceleration structures.
We have nested structures so tracking this from the descriptor
set is going to be a mess.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Jason Ekstrand
f31bfda34a util: Move the 4x4 matrix inverse function to u_math
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11078>
2021-06-18 22:16:27 +00:00
Rob Clark
1727adfbc5 freedreno/ci: Increase # of jobs for CI runners
The idea is that the tests will spend *some* time stalling waiting to
read back results from the GPU.  So use a # of jobs that is slightly
more than the # of CPUs to keep the CPUs more busy.

Locally this is dropping a bit more than a minute off a parallel
deqp-gles31 run, so turn it on across the board for a6xx.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11477>
2021-06-18 21:59:06 +00:00
Rob Clark
fc00abe46c freedreno/ci: Start longest traces first
Shave off a bit of runtime on the CI job by starting the longer traces
first.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11477>
2021-06-18 21:59:06 +00:00
Dave Airlie
714145f54c crocus/gen6: fix depth blit blorp regression.
The tesseract fix broke depth blits using blorp as depth blits
on gen6 are done using the color engine. Just disable aux
up front on the destination for this case.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11456>
2021-06-19 06:05:08 +10:00
Emma Anholt
caa5c5b12e freedreno/ir3: Move NIR printing to mesa_log.
Now we can get some NIR debug on Android.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18 18:18:35 +00:00
Emma Anholt
990c232603 nir: Add an interface for logging shaders with mesa_log*.
For debug on Android, it's useful to be able to print shaders to the
android log interface, since you don't usually have stdout/stderr.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18 18:18:35 +00:00
Emma Anholt
88fe7ab4fa freedreno/ir3: Move the native code output to mesa_log as well.
I didn't feel like rewriting ir3_shader_disasm() off of FILE *s, so use
the same trick as the disasm_info path above to write to memory and then
hand the multi-line blob off to mesa_log.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18 18:18:35 +00:00
Emma Anholt
9d458336c6 freedreno/ir3: Use mesa_log_stream() for ir3 disassembly.
This means you can get dumps on android, and output on Linux goes to
stderr.  However, this does mean that on Linux the output goes from
looking like:

AFTER: ir3_legalize:
block3276208368 {
	0000:0001:002: 	cov.u32s16 hr2.x, c2.x
	0000:0002:002: 	mov.u32u32 r0.x, c0.x
[...]

to:

MESA: info: AFTER: ir3_legalize:
MESA: info: block3405271904 {
MESA: info: 	0000:0001:002: 	cov.u32s16 hr2.x, c2.x
MESA: info: 	0000:0002:002: 	mov.u32u32 r0.x, c0.x
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18 18:18:35 +00:00
Emma Anholt
250c127c20 util/log: Add a streaming printf interface.
Often disassemblers and things in our drivers want to be able to
incrementally printf together a line, but that gets in the way of
Android's logging that wants to see a whole line all at once.  Make a
little wrapper to do the ralloc_asprintf_rewrite_tail() and flushing lines
as they appear.

Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18 18:18:35 +00:00
Emma Anholt
3863008c22 freedreno/ir3: Move the assert output to mesa_loge().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18 18:18:35 +00:00
Emma Anholt
ecf807c900 freedreno: Move some driver debug printfs to mesa_logd.
This means the logging will work on Android, and won't get mixed up in
application stdout on Linux.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9262>
2021-06-18 18:18:35 +00:00
Emma Anholt
caf69b5b77 i915g: Add triangle provoking vertex support.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11470>
2021-06-18 18:11:12 +00:00
Eric Engestrom
ddf5c798d2 docs: update calendar and link releases notes for 21.1.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11472>
2021-06-18 18:07:12 +00:00
Eric Engestrom
b8d54b7a71 docs: add release notes for 21.1.3
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11472>
2021-06-18 18:07:11 +00:00
Mike Blumenkrantz
4f86cd46eb nine: add zink to the build target
Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11467>
2021-06-18 17:44:14 +00:00
Mike Blumenkrantz
f91ffe1349 nine: only enable tgsi disk cache if the driver supports it
this crashes otherwise

Reviewed-by: Axel Davy <davyaxel0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11471>
2021-06-18 17:34:09 +00:00
Samuel Pitoiset
977355c6e5 radv: fix dynamic culling and depth/stencil related dynamic states
To avoid overwriting previous dynamic state with default state from
the pipeline.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4926
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11375>
2021-06-18 16:27:57 +00:00
Mike Blumenkrantz
651c6b16ff radv: move pipe_misaligned and l2_coherent image checks to flags set on init
this should save 4-5% cpu in some cases

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11462>
2021-06-18 16:02:26 +00:00
Boyuan Zhang
e1af22d9dd radeon/vcn: allocate non-tmz context buffer for VCN2+
By design, context buffer should be allocated as TMZ buffer for secure playback
for VCN 1 only. For VCN 2&2+, context buffer should be moved out of TMZ.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11388>
2021-06-18 14:35:44 +00:00
Boyuan Zhang
796358e2f5 radeon/vcn: move calc_dpb_size into create_decoder
Dpb buffer size calculation should based on the values provided in player's
decoder creation call. db_alignmet should be decided in decoder creation
call as well. Therefore, move db_alignment and dpb buffer size calculation
from rvcn_dec_message_decode to radeon_create_decoder function.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11378>
2021-06-18 14:23:24 +00:00
Jason Ekstrand
b97dedd365 docs/isl: Add detailed documentation about CCS compression
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
2021-06-18 13:03:48 +00:00
Jason Ekstrand
6b15ce9fa2 docs/isl: Add detailed documentation about tiling on Intel GPUs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
2021-06-18 13:03:48 +00:00
Jason Ekstrand
0f6ebd2b73 docs/isl: Add detailed documentation about isl formats
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
2021-06-18 13:03:48 +00:00
Jason Ekstrand
3894e42590 docs/isl: Document ISL's units
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
2021-06-18 13:03:48 +00:00
Jason Ekstrand
d07ec294bb isl: Document more members of isl_surf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
2021-06-18 13:03:48 +00:00
Jason Ekstrand
831750b40b docs: Begin documenting ISL
This commit mostly just adds the framework required to scrape
documentation out of the ISL sources and headers.  The method chosen
here is a combination of doxygen and breathe (a sphinx extension for
doxygen integration).  I'll freely admit that doxygen is pretty terrible
but it seems like the best option we have available to us today.

Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11366>
2021-06-18 13:03:48 +00:00
Mike Blumenkrantz
d3a63149da zink: remove inlinable_uniforms_dirty_mask
this should've always just been flagging the shaders dirty directly

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11405>
2021-06-18 12:50:03 +00:00
Mike Blumenkrantz
78f820acd7 zink: remove duplicated bitflag filtering for inline uniforms
'bits' already does this

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11405>
2021-06-18 12:50:03 +00:00
Samuel Pitoiset
60348360a2 radv: create only one pipeline for decompressing depth/stencil images
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11263>
2021-06-18 14:15:30 +02:00
Samuel Pitoiset
213c4c5f44 radv: always decompress both aspects of a depth/stencil image
If compressed rendering is only used for the depth aspect of a
depth/stencil image, stencil might also be compressed and it needs
to be decompressed. This only happens for non-TC compatible images.

As long as the driver needs to decompress the depth aspect, I don't
think that decompressing the stencil aspect introduces extra cost.

Fixes dEQP-VK.renderpass*late_fragment_tests*.d32_sfloat_s8_uint for
chips that don't support TC-compat HTILE.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11263>
2021-06-18 14:15:30 +02:00
Samuel Pitoiset
50233d0daa radv: reject binding buffer/image when the device memory is too small
From the Vulkan spec 1.2.181:
    "The difference of the size of memory and memoryOffset must be
     greater than or equal to the size member of the
     VkMemoryRequirements structure returned from a call to
     vkGetImageMemoryRequirements with the same image"

This is invalid usage but adding a check in the driver is safe and
might avoid spurious failures.

This is a workaround for the inventory GPU hang with Cyberpunk 2077
which is actually a game bug. Luckily the game handles this error
gracefully.

Since the addrlib change from March, addrlib now selects a better
swizzle mode (4KB instead of 64KB) which reduces image size. Though,
the game assumes that an image with 2 mips is always smaller than the
same image but with 6 mips. This is not always true if the swizzle mode
is different. Then, it creates a D312 heap that is too small for the 2
mips image and the GPU hang with a memory violation, ugh...

Note that next vkd3d-proton release should also reject this but
fixing both sides is fine.

Cc: 21.1 mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4823
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4593
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11448>
2021-06-18 08:04:29 +00:00
Pierre-Eric Pelloux-Prayer
66dbd16f38 radeonsi: skip instance_count==0 draws on <= GFX9
This changes seems to prevent a hang, at least on Renoir chips.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4866
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11356>
2021-06-18 09:18:47 +02:00
Vinson Lee
2624765e66 nvc0/ir: Initialize Limits members in constructor.
Fix defect reported by Coverity Scan.

Uninitialized scalar field (UNINIT_CTOR)
uninit_member: Non-static class member min is not initialized in this constructor nor in any functions that it calls.
uninit_member: Non-static class member max is not initialized in this constructor nor in any functions that it calls.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11351>
2021-06-18 05:28:06 +00:00
Vinson Lee
5f771134ad intel/vec4: Add missing break statement.
Fix defect reported by Coverity Scan.

Missing break in switch (MISSING_BREAK)
unterminated_case: The case for value
VEC4_OPCODE_ZERO_OOB_PUSH_REGS is not terminated by a break
statement.

Fixes: 89fd196f6b ("intel/vec4: Add support for masking pushed data")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11347>
2021-06-18 05:02:23 +00:00
Emma Anholt
2b3fc26da8 i915g: Switch to using nir-to-tgsi.
This fixes ~10% of the GLES2 failures thanks to having a better compiler,
though in some cases we get some new compile fails due to instr count or
uniform count.  We still have to do NIR-to-TGSI because the NIR gallivm
draw path isn't ready for non-native-integer NIR code, and st/mesa treats
native-integer as a screen property instead of a stage property.

Other than the noted regressions in the xfails, for
dEQP-GLES2.functional.uniform_api.random.74: compile fail changes reasons
triggering an aassertion instead of drawing magenta.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18 04:30:43 +00:00
Emma Anholt
934d2c8f7f i915g: Handle fragment depth being in OUT[1] not OUT[0].
Prevents regressions when switching to nir-to-tgsi which orders the
outputs differently.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18 04:30:43 +00:00
Emma Anholt
026452fe46 nir_to_tgsi: Support integer sysvals on !CAP_INTEGERS hardware.
glsl_to_tgsi does the same thing, needed for the draw path on i915g.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18 04:30:43 +00:00