Commit graph

141701 commits

Author SHA1 Message Date
Emma Anholt
baa8d33908 nir_to_tgsi: Fix internal handling of NIR uints for !CAP_INTEGERS
If we called nir_lower_int_to_float(), then ALU-consumed ints got turned
into floats and we have to interpret them that way.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18 04:30:43 +00:00
Eric Anholt
47804f53f9 nir: Do peephole select on other instructions if the limit is ~0.
limit==0 is the signal for "don't peephole anything but a move that will
be optimized aways."  limit > 0 is "up to N alu instructions may be moved
out."  nir-to-tgsi uses ~0 as the indicator of "No, we really need to
eliminate all if instructions" on hardware like i915 that doesn't have
control flow.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18 04:30:43 +00:00
Emma Anholt
aba8b6675a nir/lower_int_to_float: Make sure the cursor is in the right spot.
We need to make get it updated after we may have nir_instr_remove()d an
instruction, and when we cross blocks.  This didn't really matter before
because the only builder usage was idiv, which other users of
lower_int_to_float were probably never hitting.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18 04:30:43 +00:00
Emma Anholt
31ab2735db i915g: Allow fragment coord conventions TGSI properties to be set.
The frontend lowering handles normalizing the conventions to the only
model we support, we just need to ignore the property in the TGSI.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18 04:30:43 +00:00
Emma Anholt
942f62a9b2 i915: Drop assertion failure about seeing each const decled once.
nir_to_tgsi sometimes emits multiple decls currently, but we don't
actually care because we're just checking which ones are live.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18 04:30:43 +00:00
Emma Anholt
7378c64792 i915: Disable vertex texturing and delete the code.
It's not a required feature of the GL2.1 or GLES2, and you really don't
want to be doing SW VS access of the write-combined texture data.  Also,
avoids memory corruption in deqp:

Test case 'dEQP-GLES2.functional.texture.vertex.cube.filtering.linear_mipmap_nearest_linear_repeat'..
Mesa: User error: GL_INVALID_ENUM in glGetIntegerv(pname=GL_MAJOR_VERSION)
  Fail (Image comparison failed)

Test case 'dEQP-GLES2.functional.fragment_ops.depth_stencil.stencil_depth_funcs.stencil_equal_depth_always'..
==559181== Invalid read of size 4
==559181==    at 0x641E8D0: i915_drm_buffer_unmap (i915_drm_buffer.c:204)
==559181==    by 0x64151EB: i915_cleanup_vertex_sampling (i915_state.c:449)
==559181==    by 0x640AEA7: i915_draw_vbo (i915_context.c:134)
==559181==    by 0x640AEA7: i915_draw_vbo (i915_context.c:55)
==559181==    by 0x61367B1: cso_draw_vbo (cso_context.c:1524)
[...]

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11329>
2021-06-18 04:30:43 +00:00
Yiwei Zhang
87f35032a6 anv: enable multi-planar support for drm format modifier
This patch only enables the below VkFormat:
- VK_FORMAT_G8_B8R8_2PLANE_420_UNORM

This patch ensures the proper behavior of the below APIs:
- vkGetPhysicalDeviceFormatProperties2
- vkGetPhysicalDeviceImageFormatProperties2
- vkCreateImage
- vkGetImageSubresourceLayout
- vkGetImageDrmFormatModifierPropertiesEXT
- vkGetImageMemoryRequirements
- vkGetImageMemoryRequirements2

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
2021-06-18 01:04:15 +00:00
Yiwei Zhang
ec70092d55 anv: support multi-planar format in add_all_surfaces_explicit_layout
Add initial multi-planar format support on the images with modifiers:
- With aux usage,
  - Format plane count must be 1.
  - Memory plane count must be 2.
- Without aux usage,
  - Each format plane must map to a distinct memory plane.

For the other cases, currently there is no way to properly map memory
planes to format planes and aux planes due to the lack of defined ABI
for external multi-planar images.

This patch doesn't include some potentially supported cases like all
format planes mapping to a single memory plane, additional refactoring
is needed to workaround explicit base offset + ANV_OFFSET_IMPLICIT.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
2021-06-18 01:04:15 +00:00
Yiwei Zhang
345a4e9871 anv: fix some log formats
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chad Versace <chad@kiwitree.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11281>
2021-06-18 01:04:15 +00:00
Emma Anholt
6bce24e214 freedreno: Add some cheza flakes from the last week.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11453>
2021-06-17 23:06:18 +00:00
Emma Anholt
df7fdae127 freedreno: Skip staging blits from uninitialized resources.
When storing depth- or stencil-only texture data that has been packed into
a depth/stencil texture, the tex store gets PIPE_MAP_READ added onto it
since the other channel will get ORed into the incoming data, but
sometimes we know that the other component is undefined because the whole
texture is either fresh or just invalidated.

Cleans up a confusing extra blit in a dEQP case I've been debugging, and
should be less work for dEQP CI.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
2021-06-17 22:47:51 +00:00
Emma Anholt
4018c5f928 freedreno: Add more detailed blit debug in FD_MESA_DEBUG=msgs.
For debugging the batch cache, it really helps to see the blits that
happen, and which are staging blits in the transfer map process.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
2021-06-17 22:47:51 +00:00
Emma Anholt
8effbeeea6 freedreno/fdl: Give the tiling mode a nice name in debug dumps.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
2021-06-17 22:47:51 +00:00
Emma Anholt
57da290b52 freedreno: Move FD_MESA_DEBUG=msgs output to mesa_logi.
It didn't work unless you had a debug build, and I regularly want to use
it on non-debug builds.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
2021-06-17 22:47:51 +00:00
Emma Anholt
d4203bf7ab freedreno: Add perf_debug() for our software conditional rendering.
We could do it in hardware, and turnip does, but it hasn't bubbled up our
priorities yet.  At least make it more discoverable when you stumble over
it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11452>
2021-06-17 22:47:51 +00:00
Rob Clark
6402dc17b3 freedreno: Defer freeing batch->key
We use the same key in autotune to track historical data about a given
framebuffer state, to inform the decision about using gmem vs sysmem
rendering.  Which means we need the key to stick around during the
flush, even if the batch is removed from the batch-cache before the
flush.

Fixes: 507f701d9e ("freedreno: Fix batch flush race condition")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11450>
2021-06-17 14:01:36 -07:00
Caio Marcelo de Oliveira Filho
64cb143b92 spirv: Fix handling of OpBranchConditional with same THEN and ELSE
When an OpBranchConditional that had two equal branches was parsed, we
were treating it as a regular OpBranch.  However this doesn't work
well when there's an associated OpSelectionMerge.  We ended up
skipping marking the merge block as such, and depending on what was
inside the construct we would end up trying to process the block
twice.

Fix this by keeping the vtn_if around, but when emitting NIR identify
the two equal branch case.

Fixes: 9c2a11430e ("spirv: Rewrite CFG construction")
Closes: #3786, #4580
Reviewed-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9297>
2021-06-17 20:05:39 +00:00
Icecream95
38e8d7afe3 pan/mdg: Fix reading a spilt register in the bundle it's written
Read directly from the instruction getting spilt. Otherwise a fill
will be inserted before the spill writing the value, so the
instruction reading the spilt value gets garbage data.

Use the bundle_id to check if the instructions are in the same bundle.

Insert a move instruction, as the spill needs the value in a LD/ST
register such as AL0, while the ALU instruction reading the value
needs it in a work register such as R0.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4857
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
2021-06-17 19:53:14 +00:00
Icecream95
31d26ebf1b pan/mdg: Fill from TLS before spilling non-SSA nodes
Otherwise the data already written to the node will get overwritten.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
2021-06-17 19:53:14 +00:00
Icecream95
ed9a9a09f2 pan/mdg: Reorder some code in mir_spill_register
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
2021-06-17 19:53:14 +00:00
Icecream95
1490e7e622 pan/mdg: Add a bundle ID to instructions
So that it is possible to check if two instructions were scheduled
into the same bundle.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11212>
2021-06-17 19:53:14 +00:00
Rob Clark
3e3ec59895 freedreno/a6xx: Skip nv_copy_image tests
These look pretty redundant with arb_copy_image, so skip to keep CI
runtime reasonable.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
2021-06-17 19:34:51 +00:00
Rob Clark
fff2aa46a7 freedreno/a6xx: Flip on copy_image
Now that we have the rest of format "casting" sharp edges sorted, flip
on copy_image and gles32.

Unfortunately it adds back to piglit xfails (but at least that is more
than offset by my previous round of piglit fixes, and these are pretty
much all things we know had issues based on corresponding nv_copy_image
tests).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
2021-06-17 19:34:51 +00:00
Rob Clark
6ca9f4f5ca freedreno: Fix for multi-draw blits
We have some logic to detect when u_blitter generated draws overwrite
the entire render-target, so we know we can discard anything previous.
But some blits (like multi-sample) do multiple draws.  We don't want to
discard the earlier draws from the same blit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
2021-06-17 19:34:51 +00:00
Rob Clark
9629f3aa46 freedreno/a6xx: Handle u/snorm vs u/sint validation
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
2021-06-17 19:34:51 +00:00
Rob Clark
678e4842cc freedreno/a6xx: Use UNORM for SNORM copy blits
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
2021-06-17 19:34:51 +00:00
Rob Clark
70d571e558 freedreno/blitter: Flush before self-blits
In paths where we are handling blits on the 3d pipe, if src==dst we need
to flush to ensure what gets sampled by the blit shader reflects the
results of any previous blits.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
2021-06-17 19:34:50 +00:00
Rob Clark
2f29425a0a freedreno: Fix flushes with NULL batch
Sequences that pctx->set_framebuffer_state() before pctx->flush() will
see ctx->batch being NULL.. but they still need to call fd_bc_flush(ctx)
to ensure pending batches associated with the context are flushed.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11402>
2021-06-17 19:34:50 +00:00
Iván Briano
4c67924251 intel/nir: Fix txs for null surfaces
Closes: #4860
Fixes: 05a37e2422 ("intel/nir: Set lower txs with non-zero LOD")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11435>
2021-06-17 11:55:22 -07:00
Emma Anholt
ac9ae97d30 freedreno: Flush batches upon destroying the ctx.
The invalidate would take it out of the bc tracking, so you could go
allocate a new batch->idx matching this one, while this one is still in
the bc using that idx.

You can't generate any new rendering with the ctx's old batches at this
point, anyway, so just flush for simplicity.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
2021-06-17 09:11:57 -07:00
Emma Anholt
2a9225d05f freedreno: Remove broken back_blit optimization.
It wasn't checking that the transfer map would definitely overwrite all of
the data being initialized by the back blit, and if we knew that it
would then the caller would have provided PIPE_MAP_DISCARD_WHOLE_RESOURCE.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
2021-06-17 09:11:02 -07:00
Emma Anholt
09e1fb2bce freedreno: Move the !MAP_WRITE write batch refcounting to the branch.
For MAP_WRITE, we flush all the batches referencing the BO, so the write
batch will get flushed anyway.  No need to take an extra ref.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
2021-06-17 09:11:02 -07:00
Emma Anholt
fd571565d2 freedreno: Fix batch reference handling in flush_resource().
We take references under the lock, but then accessed the lock-requiring
batch_cache structure without holding the lock.  The batches wouldn't get
freed and removed from their slots until the last ref goes away so it was
safe (other than the assert at the end), but writing the simple code is
shorter and requires fewer assumptions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11439>
2021-06-17 09:11:02 -07:00
Iago Toral Quiroga
cf2747e7ac v3dv: implement VK_EXT_index_type_uint8
Relevant CTS tests:
dEQP-VK.pipeline.input_assembly.*.index_type_uint8.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11444>
2021-06-17 12:26:44 +00:00
Charlie
d9c53c50ad v3dv: enable ASTC formats
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11336>
2021-06-17 11:33:06 +00:00
Charlie
26a7afc94f v3dv: add ASTC formats to get_compatible_tlb_format
CTS doesn't seem to hit this, but they're all 128bit formats so this
should be right

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11336>
2021-06-17 11:33:06 +00:00
Charlie
56bf92ff0b v3dv: divide by block size in copy_image_blit
This handles compressed formats with non-4x4 blocks, like ASTC.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11336>
2021-06-17 11:33:06 +00:00
Charlie
6756f55c84 v3dv: add the unswizzled RGBA4444 format
If we're supporting the R/B swapped one we might as well support the one that
isn't.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11336>
2021-06-17 11:33:06 +00:00
Gert Wollny
8aaa08844f r600/sfn: Clean up some ALU lowering and move code
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
2021-06-17 10:53:52 +00:00
Gert Wollny
82c076d2c3 r600/sfn: Don't read return values of atomic ops that are not used
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
2021-06-17 10:53:52 +00:00
Gert Wollny
800bfefde5 r600/sfn: Drop method for emit_atomic_add, it is handled in generic code
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
2021-06-17 10:53:52 +00:00
Gert Wollny
2e8901a072 r600/sfn: don't read back unused image atomic result values
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
2021-06-17 10:53:52 +00:00
Gert Wollny
5e1a703934 r600/sfn: don't designates initializers, since they are c++20
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11348>
2021-06-17 10:53:52 +00:00
Kai-Heng Feng
f9d8d9acbb iris: Avoid abort() if kernel can't allocate memory
When the system doesn't have enough memory, GNOME Shell may be crashed
by iris:
gnome-shell[1161]: iris: Failed to submit batchbuffer: Cannot allocate memory
gnome-shell[1161]: GNOME Shell crashed with signal 6

So don't abort() when kernel can't allocate memory to avoid crashing the
entire desktop.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11178>
2021-06-17 09:04:17 +00:00
Iago Toral Quiroga
d873e30d3b v3dv: expose VK_KHR_shader_non_semantic_info
This is entirely implemented in the SPIR-V frontend.

Relevant CTS tests:
dEQP-VK.spirv_assembly.instruction.compute.non_semantic_info.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11440>
2021-06-17 08:49:16 +00:00
Pierre-Eric Pelloux-Prayer
0fd152dab3 disk_cache: use UTIL_QUEUE_INIT_SCALE_THREADS
Instead of spawning 4 threads when the cache is created,
spawn 1 and let u_queue grow the number of threads if
needed.

I wrote this patch because when running piglit's quick_shader
profile I had lots of samples in disk cache threads - mostly
in native_queued_spin_lock_slowpath kernel function.

Since these tests shouldn't really stress the cache, I assumed
it was caused only by thread creations.

After writing the patch and redoing the measurement, I got an
improvement but I still more hits in the same function for
shader_runner:$disk0 thread so something was wrong.

After digging more, I found out that my shader cache index was
corrupted: the on-disk size was 29MB but the index reported it
was way more than 1GB. So each disk cache thread was spending
a lot of time trying to evict files. Given that my cache had
a really low count of files, the LRU method based on randomly
generating subfolder names failed, so evicting was very slow.

Now that my cache index is fixed, the disk cache threads are
mostly idle but I still think it makes sense to grow the
number of threads instead of spawning 4 at the program start.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
2021-06-17 09:11:59 +02:00
Pierre-Eric Pelloux-Prayer
3713dc6b2a util/u_queue: add UTIL_QUEUE_INIT_SCALE_THREADS flag
This flag allow to create a single thread initially, but set
max_thread to the request thread count.

If the queue is full and num_threads is lower than max_threads,
we spawn a new thread to help process the queue faster.

This avoid creating N threads at queue creation time.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
2021-06-17 09:11:59 +02:00
Pierre-Eric Pelloux-Prayer
0c88df1f6a util/u_queue: move function definition up
Will be used by the next commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
2021-06-17 09:11:58 +02:00
Pierre-Eric Pelloux-Prayer
edb77ec3c7 radeonsi: delay sample_pos_buffer creation until first use
And use pipe_buffer_create_with_data instead of doing it
manually.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
2021-06-17 09:10:29 +02:00
Pierre-Eric Pelloux-Prayer
84dca32c51 vbo: delay vbo_exec_vtx_map call
Instead of doing vbo_exec_vtx_map during initialization,
defer it until the first actual user.

v2: move init to vbo_exec_wrap_upgrade_vertex (Emma Anholt)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11296>
2021-06-17 09:10:29 +02:00