Commit graph

141701 commits

Author SHA1 Message Date
Dave Airlie
7399d6028f crocus: Avoid replacing backing storage for buffers with no contents
Ported 97e9de1795 from iris

    We might get asked to pitch the storage on a buffer that already has
    no meaningful contents.  In this case, the existing buffer is as good
    as a new one.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>
2021-06-24 06:50:49 +00:00
Dave Airlie
0fa4b64f6c crocus: dirty blend state more often.
The blend state depends on wm_prog_data dual_src and it also
depends on the cbuf formats in can_emit_logic_op.

Dirty it in the correct places.

Fixes:
dEQP-GLES3.functional.fbo.invalidate*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>
2021-06-24 06:50:49 +00:00
Dave Airlie
a74c16e5f8 crocus/gfx6: fix sampler view first level.
The gfx6 state needs to dirty sampler state so that BaseMipLevel
gets updated properly.

Fixes:
dEQP-GLES3.functional.texture.mipmap.cube.base_level.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>
2021-06-24 06:50:49 +00:00
Dave Airlie
0acd202858 intel/genxml: fix gfx6 GS SVB_INDEX encoding
This seems to match what the docs + 965 traces say

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>
2021-06-24 06:50:49 +00:00
Dave Airlie
c282a082be crocus/query: poll the syncobj in the no wait situation
In the no wait, poll the syncobj and bail if it's hasn't signalled.
This fixes a bunch of deqp xfb tests on sandybridge

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11567>
2021-06-24 06:50:49 +00:00
Adam Jackson
9ca6abd424 vl/dri3: Don't leak regions on the X server
I can't tell from a quick read whether this clip region is actually just
the bounding box so could be skipped entirely. But the old code never
destroyed it, which means we'd leak a couple hundred bytes on the X
server side for every SwapBuffers until the client dies of XID
exhaustion, which is somewhere north of 2GB for typical systems so you
may or may not just run out of memory first.

Create the region at swap time and stash it in the drawable state.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11461>
2021-06-24 03:18:06 +00:00
Adam Jackson
7e9424d91b loader/dri3: Don't churn through xfixes regions in SwapBuffers
Regions are not expensive objects on the server side, it's very slightly
cheaper to update an existing one than to create a new one, and we can
garbage collect them when the drawable is destroyed. Worse, XID reuse
bugs exist, so the more we can do to not churn through XIDs the better.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11461>
2021-06-24 03:18:06 +00:00
Adam Jackson
34e4622983 loader/dri3: Properly initialize the XFIXES extension
The server starts off assuming the only XFIXES request the client might
known is FixesQueryVersion, and based on the version number the client
supplies it unlocks additional requests. If you forget to do this then
xcb_xfixes_create_region will throw BadRequest and you will be very
confused. libXfixes would hide this for you in extension setup but xcb
is not so forgiving.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11461>
2021-06-24 03:18:06 +00:00
Marek Olšák
888b7ba338 radeonsi: optimize set_inlinable_constants when they don't change
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>
2021-06-23 22:37:34 -04:00
Marek Olšák
86355b5984 ac/gpu_info: adjust the condition for use_late_alloc
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>
2021-06-23 22:37:32 -04:00
Marek Olšák
ff42fd1fdf radeonsi: don't use NGG culling on 1 RB chips
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>
2021-06-23 22:37:31 -04:00
Marek Olšák
f7afcc3d11 radeonsi: remove incorrect comment about hangs in gfx10_ngg_gs_emit_epilogue
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>
2021-06-23 22:37:29 -04:00
Marek Olšák
593f3b3a5a radeonsi: if shader culling culls all vertices, cull the primitive exports too
This was overlooked. It benefits triangle strips the most due to
GS fast launch.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>
2021-06-23 22:37:27 -04:00
Marek Olšák
defc7c92d9 radeonsi: document why VBO descriptors in user SGPRs are beneficial
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11509>
2021-06-23 22:37:23 -04:00
Mike Blumenkrantz
f99f7c06e7 lavapipe: implement multidraw ext
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11533>
2021-06-24 01:35:33 +00:00
Mike Blumenkrantz
be0e34450b zink: use depth/stencil-only layouts for depth/stencil-only formats
just kidding, this is banned by spec

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11389>
2021-06-24 01:19:07 +00:00
Timothy Arceri
d22cdcd33a util: add work around for the game We Happy Few
This is another Unreal engine game that requires the
allow_glsl_cross_stage_interpolation_mismatch workaround.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4966

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11558>
2021-06-23 23:44:33 +00:00
Emma Anholt
a067f54f3e ci/i915g: Skip the piglit glx tests since we're not running X.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11559>
2021-06-23 19:54:55 +00:00
Emma Anholt
1ccb8ab801 i915g: Finish out blend factor overrides for both RGBx and A8.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11559>
2021-06-23 19:54:55 +00:00
Emma Anholt
2683c7bf9a i915g: Fix bad naming of depth texture formats.
Now matches classic's i915_reg.h and the spec.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11559>
2021-06-23 19:54:55 +00:00
Connor Abbott
078030973b ir3/ra: Fix corner case in collect handling
I ran into this when accidentally changing the scheduling order in the
hl2 trace.

Fixes: 0ffcb19 ("ir3: Rewrite register allocation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
3dc8c59858 ir3: Remove IR3_REG_DEST
This was needed because code iterating the regs array needed to know
what was a destination and what wasn't, but now we have separate srcs
and dsts arrays so it's not needed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
def96adaee ir3: Remove regs array
Now that everything is converted over, switch to separate src/dst
arrays.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
57aeef5c13 ir3/frontend: Switch to srcs/dsts arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
5785abb9ed ir3/opts: Switch to srcs/dsts arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
58fb0a01e1 ir3/validate: Switch to srcs/dsts arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
050ec77d1b ir3/print: Switch to srcs/dsts arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
1b4990eea6 ir3/legalize: Switch to srcs/dsts arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
abebc1f53f ir3/array_to_ssa: Switch to srcs/dsts arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
dd13081e03 ir3/parser: Switch to srcs/dsts arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
af48cfc06b ir3/ra: Switch to srcs/dsts arrays
RA was manually fiddling with regs to copy over the parallel copy code,
which has to be done in a different way, but if we switch this all over
at once it shouldn't be a problem.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
d3e08327cf ir3/core: Switch to srcs/dsts arrays
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
50994eeabf ir3/sched: Convert to srcs/dsts arrays
Also change the indexing in ir3_delayslots, so it's finally sane! To do
this we also have to change foreach_ssa_src_n to index srcs instead of
regs, so that the indexing stays in sync.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
132dfacdcb freedreno/tests: Convert to srcs/dsts
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
bff83fc42b freedreno/isa: Convert to srcs/dsts
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
db7814ad56 ir3: Add srcs/dsts arrays to ir3_instruction
Initially these will shadow regs, so that we can transition things
before getting rid of regs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
59b9935877 ir3/legalize: Construct branch properly
Don't just yeet stuff into regs without updating regs_count, etc. This
will break horribly during the transition otherwise.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
e93f15d4bc ir3: Add separate src/dst count in ir3_instr
srcs and dsts will be in separate arrays, so we need everything creating
it to give a separate source and dest max count.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
3071e2e933 ir3: Split ir3_reg_create() into ir3_{src,dst}_create()
Right now they are basically the same, but in the future they will
append to different arrays.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
9af795d9b9 ir3: Make ir3_instruction::address a normal register
This fixes an annoying mismatch in the indices between foreach_ssa_src_n
and ir3_delayslots(), and lets us remove a bunch of other special cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
2522f387a3 ir3: Add is_reg_special()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
dce680737d ir3: Validate that ir3_register::instr is correct
Catch the mistake fixed in the previous commit.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
ef7bc4a2aa ir3: Update ir3_register::instr when cloning instructions
We happened to not clone any SSA instructions, but we will once address
instructions start counting as SSA. Fix this oversight.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
0f329ba10a ir3: Split read-modify-write array dests in two
Instructions that operate on an array read the previous state of the
array, modify it, and write a new array, at least conceptually before
RA. Previously the same register specified the previous state and acted
as the new state, but this meant that it was both a source and
destination which meant that it was getting in the way of splitting up
sources and destinations. Break out the source into a separate register,
and use the new tied-src infrastructure to share code with a6xx atomics.
With this, there are basically no more special cases for arrays in RA.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Connor Abbott
cc64945336 ir3: Make tied sources/destinations part of the IR
Previously this was hard-coded for a6xx atomic instructions. However
we'll need a way for array destinations to point to the source with the
previous value of the array when we split them up. This is conceptually
the same as tied source/destinations for a6xx atomics, except that array
writes sometimes won't have a previous value to point to. So move this
into the IR so that it can be more dynamic. As a bonus we can move the
knowledge of a6xx atomics out of RA, where it's out-of-place, and into
the a6xx-specific code that creates them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11469>
2021-06-23 17:20:29 +00:00
Daniel Schürmann
f953dc2ced amd/ci: add hawaii-specific skip and fail lists
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10424>
2021-06-23 15:17:22 +00:00
Icecream95
08495a948e pan/mdg: Add 16 bytes of padding to the end of shaders
Fixes INSTR_INVALID_PC faults when a shader ends on a 16MB boundary.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11551>
2021-06-23 14:42:55 +00:00
Tapani Pälli
55951ac28e anv: fix emitting dynamic primitive topology
Initial implementation missed various fields that derive from the
primitive topology. This patch fixes 3DSTATE_RASTER/3DSTATE_SF,
3DSTATE_CLIP and 3DSTATE_WM (gen7.x) emission in the dynamic case.

Fixes: f6fa4a8000 ("anv: add support for dynamic primitive topology change")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4924
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11379>
2021-06-23 12:01:45 +00:00
Daniel Stone
43b99e48b1 Revert "ci: disable panfrost t760 jobs"
Both our T760 machines took a dive in beautiful synchronicity last
night, were recovered early this morning.

This reverts commit 854d93f73d.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11555>
2021-06-23 12:30:07 +01:00
Tapani Pälli
2d87ea3166 iris: take a reference to memobj bo in iris_resource_from_memobj
v2: and remove it from iris_memobj_create_from_handle ... (Nanley)

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4969
Fixes: 772dc50d16 ("iris: hook up resource creation from memory object")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11552>
2021-06-23 10:46:09 +00:00