Commit graph

203655 commits

Author SHA1 Message Date
Collabora's Gfx CI Team
1ce0cef6bf Uprev ANGLE to 1b34d2a18af12cc55a3bc74dd679c2937d10cc5c
6abdc11741...1b34d2a18a

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34277>
2025-04-01 12:51:06 +00:00
Daniel Stone
3b6a40af53 ci: Make all job timeouts explicit
Enforce a default job timeout of 1 second, to make jobs which don't
explicitly specify a timeout insta-fail, rather than potentially hanging
around for an hour.

Container builds get the full hour as they can run long and are not run
in pre-merge context, and LAVA jobs also get the full hour as they have
multiple internal timeout mechanisms which aim to fast-fail jobs once
they actually start. However, as they just queue jobs to an external
host (shared with other projects like KernelCI), these timeouts aren't
reflected into the GitLab CI definitions.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:01 +00:00
Daniel Stone
3fee0ef129 ci/microsoft: Add job timeouts and pin Piglit to GSt
quick_shader is for some reason now excruciatingly slow on the Microsoft
runners, but fine on the GStreamer runners. Until we can figure out why
this is happening - 27min runtimes instead of 3min - just keep them over
there.

Dozen is miraculously unaffected.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:01 +00:00
Daniel Stone
370efffe10 ci/docs: Add timeout to doc build
Give these about double the time they usually take to complete.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:01 +00:00
Daniel Stone
1be1af78bf ci/virgl: Add timeout to software jobs
Let's make sure these don't get stuck. They're all good citizens and
turn around in 5min or less, so give them triple that.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:01 +00:00
Daniel Stone
3911cb85bf ci/llvmpipe: Add llvmpipe and lavapipe timeouts
These jobs all pretty comfortably complete in 5-7min. Add a timeout for
roughly double that to make sure that jobs don't get stuck.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:01 +00:00
Daniel Stone
cab69e51f3 ci/softpipe: Add timeouts to softpipe jobs
Make sure we don't get stuck somewhere and fail merges.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:01 +00:00
Daniel Stone
afee7921cb ci: Reduce build job timeouts
Most of our build jobs have had a timeout of 1 hour since 6425b6e3d4,
which pushed the timeout as high as possible to allow for LTO building
taking forever. Since then, we've pulled LTO back to only running on the
fedora-release nightly job.

This tries to bring us back to the ideal from 322a83f321, where the
build jobs all have very low timeouts both for the overall job as well
as the build section we run. So if anything goes wrong - apart from
fedora-release - we'll just assume the runner has some environmental
damage, give up, and try again.

Of the build-for-tests jobs, all but the ASan and UBSan jobs regularly
complete in around 5 minutes, apart from debian-testing which is our
critical-path build job for almost all x86-64 testing. This is obviously
not good, but is tracked in mesa#12544.

The build-only jobs not using sanitizers also typically complete in
3-4 minutes, with the exception of debian-clang-release and
debian-x86_32 which are closer to 10 minutes. That's not ideal, but
they're also not currently on the critical path, so we can live with
that.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:01 +00:00
Daniel Stone
c793f612fc ci/panfrost: Split inherit definitions into -inc
Follow what everyone else did to have gitlab-ci.yml for concrete job
definitions, and gitlab-ci-inc.yml for things which get inherited.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:01 +00:00
Daniel Stone
777dfb4062 ci/windows: Don't copy non-existent libglapi.dll
It was removed with 44bda7c258.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:01 +00:00
Daniel Stone
a9f87ff0bd ci/amd: Disable radv-fossils
This job is currently broken due to the lack of git in the Vulkan
container; it should really be pulling the fossils from S3 like the
traces anyway.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34280>
2025-04-01 12:21:00 +00:00
Robert Mader
c0ec35bb42 gallivm: Re-add check for passmgr before disposing it
Some checks are pending
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In can be NULL, but on LLVM >= 15 lp_passmgr_dispose() is
a no-op.

Fixes: 47cd0eee26 (gallivm: create a pass manager wrapper.)

Signed-off-by: Robert Mader <robert.mader@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34312>
2025-04-01 11:37:15 +00:00
Lucas Stach
d738b3ea2b etnaviv: split PIPE_BUFFER resources from other types of resources
Buffer resources are quite special as they are only one dimensional,
always linear, don't have miplevels or array slices, never have a
texture or render compatible sibling, don't ever use TS.

The gallium context interface acknowledges this fact by providing
separate entry points for buffer maps/unmaps/flushes.

Provide a specialized etna_buffer_resource as a much more lightweight
alternative to the fullblown etna_resource and implement buffer
maps/unmaps in the same straight forward, direct map manner that is
hidden inside all the tiling, TS and resource sibling handling in
etna_transfer_map/unmap. It is expected that further map optimizations
can be added on top of this simple implementation much more easily
than in the merged buffer/texture transfer code.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34061>
2025-04-01 10:09:28 +00:00
Lucas Stach
d46a8c32b5 etnaviv: use pipe_resource in etna_resource_status
This aligns the prototype with etna_resource_used and allows to
track different resource specializations in the same datastructure.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34061>
2025-04-01 10:09:28 +00:00
Rebecca Mckeever
69a08fd9b2 panvk: Support shaderImageGatherExtended
Some checks are pending
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Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34033>
2025-04-01 08:04:32 +00:00
Rebecca Mckeever
f450807b68 panvk: Remove lower_tg4_broadcom_swizzle from panvk_preprocess_nir()
We are already applying the .bagr swizzle in bifrost_preprocess_nir(), so
remove lower_tg4_broadcom_swizzle from nir_lower_tex_options in
panvk_preprocess_nir to avoid applying the swizzle twice.

Fixes: 4050697a8f ("panvk: So more nir_lower_tex before descriptor lowering")

Signed-off-by: Rebecca Mckeever <rebecca.mckeever@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34033>
2025-04-01 08:04:32 +00:00
Marek Olšák
5e02621a8a amd/addrlib: remove the DCC page fault workaround
It doesn't cause page faults anymore.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34099>
2025-04-01 03:23:22 -04:00
Marek Olšák
f0e6d86f4e amd: update addrlib
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34099>
2025-04-01 03:23:22 -04:00
Samuel Pitoiset
902c76b3be radv/ci: remove all skips for STONEY
Some checks are pending
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Seems fine too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34301>
2025-04-01 06:58:50 +00:00
Samuel Pitoiset
cb1144145a radv/ci: stop skipping one memory test due to timeouts
It seems fine now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34301>
2025-04-01 06:58:50 +00:00
Samuel Pitoiset
71b49aecdc radv: switch back radeon_cmdbuf to use 32-bit counters
This has been tested again with vkoverhead on 4 different CPUs and
using 32-bit counters is the fastest combination overall.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34229>
2025-04-01 06:18:28 +00:00
Samuel Pitoiset
f0b3a6f9d4 radv: rework command buffer emission with begin/end sequences
A begin/end sequence is something like (it's all macros based):

   radeon_begin(cs);
   radeon_emit(PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));
   radeon_emit(vertex_count);
   radeon_emit(V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque);
   radeon_end();

This is loosely based on RadeonSI (see !8653 (a0978fff)) and it seems
indeed faster overall.

The main goal of this rework is to re-use the same logic as RadeonSI
for paired packets on GFX12 (also GFX11 dGPUs) because it's supposed
to be way faster, especially on GFX12 where the CP is slow. The other
goal is to share more cmdbuf emission between both drivers in the near
future.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34229>
2025-04-01 06:18:28 +00:00
Jordan Justen
d3ec467031 intel/dev: Add BMG 0xe211 PCI ID
Some checks are pending
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Backport-to: 25.0
Ref: bspec 68090
Ref: https://patchwork.freedesktop.org/series/146769/
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34249>
2025-04-01 04:11:07 +00:00
Faith Ekstrand
e612e840d2 nak: Use is_volta() instead of sm == 70
Some checks are pending
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This is a bug fix but Volta is currently disabled by default and it only
affects fp64 and fp16.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34302>
2025-04-01 00:01:05 +00:00
Faith Ekstrand
77eb070465 nak: Add GPU generation helpers
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34302>
2025-04-01 00:01:05 +00:00
Faith Ekstrand
e2fccc1488 nak: Move sched_common.rs to reg_tracker.rs
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34302>
2025-04-01 00:01:05 +00:00
Faith Ekstrand
24a8795946 nak: Move latency information into the per-SM files
This is probably a little more code but we're about to add real data for
Turing+ so it's better to have things contained like this.  Since Volta
and earlier will always remain hacks, we might as well have those hacks
in the per-SM files rather than pretending we have a general thing in
sched_common.rs.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34302>
2025-04-01 00:01:05 +00:00
Faith Ekstrand
64ff3e8cb8 nak: Move exec_latency into the per-SM files
It's split cleanly along the SM70 boundary anyway so there's no code
duplication happening here.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34302>
2025-04-01 00:01:05 +00:00
Faith Ekstrand
ae842b5fe1 nak: Move SM70 encoding and legalize to a separate file
We're about to add instruction latencies which are going to be in their
own files because they're also massive.  This makes things follow a bit
more of a module structure where sm70.rs is the thing that ties it all
together, sm70_encode.rs is the encoder, and smXX_instr_latencies.rs
will be the individual latency files.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34302>
2025-04-01 00:01:05 +00:00
Faith Ekstrand
8e2e1e43fa nak: Add latency helpers to ShaderModel and use them
For now, these all just call into sched_common.rs but this gives us the
interface we really want going forward.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34302>
2025-04-01 00:01:05 +00:00
Faith Ekstrand
3112fbcc56 nak: Add and use a ShaderModel::needs_scoreboard() helper
For now, this is just !Op::has_fixed_latency() but this is actually the
question the scheduling code is asking.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34302>
2025-04-01 00:01:05 +00:00
Faith Ekstrand
d134379631 nak: Move has_fixed_latency to Op
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34302>
2025-04-01 00:01:05 +00:00
Dave Airlie
5d6d167a7c gallivm: check for avx512vbmi and tell LLVM the correct answer.
Some checks are pending
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There are some CPUs out there which don't have vbmi and do have
other avx512 and mesa crashes on those with illegal instructions.

This was reported to Red Hat support.

Cc: mesa-stable
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34282>
2025-03-31 21:46:45 +00:00
Lionel Landwerlin
4ac900b5bf anv/genxml: use special genX video pack files
Before:

   30453 ./build/src/intel/genxml/gen125_pack.h

After:

   17026 ./build/src/intel/genxml/gen125_pack.h
   21589 ./build/src/intel/genxml/gen125_video_pack.h

The idea is to have fewer line to parse in each genX_*.c file.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:56 +03:00
Lionel Landwerlin
4fdf5618f9 intel/genxml: add MI_FLUSH_DW to blitter engine
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:53 +03:00
Lionel Landwerlin
79a463e40b intel/genxml: define post-sync operations for MI_FLUSH_DW
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:50 +03:00
Lionel Landwerlin
d4899b0486 intel/genxml: fixup engine filtering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:47 +03:00
Lionel Landwerlin
04b6eeba63 intel/genxml: add more engine tagging on instructions
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:42 +03:00
Lionel Landwerlin
891965a471 intel/genxml: remove ISA fields
Those are for the compiler afaict.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:07 +03:00
Caio Oliveira
71ae31dbd8 intel/executor: Allow selecting a device to use
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Add a command line option `-d DEVICE` to select
a device either by index or by substring of the
name.

Use `-d list` to print available devices.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34267>
2025-03-31 19:20:10 +00:00
Caio Oliveira
9b2b3255e1 intel/executor: Use getopt for command line arguments
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34267>
2025-03-31 19:20:10 +00:00
Patrick Lerda
1db8825597 radeonsi: fix clear_depth_stencil refcnt imbalance
After ca09c173f6, util_blitter_clear_render_target() requires
a call to util_blitter_save_fragment_constant_buffer_slot().
The radeonsi implementation was using the same sequence with
util_blitter_clear_depth_stencil() which does not need this
call. This was the cause of the refcnt imbalance.

For instance, this issue is triggered with:
"piglit/bin/ext_clear_texture-stencil -auto -fbo"
while setting GALLIUM_REFCNT_LOG=refcnt.log.

Fixes: ca09c173f6 ("gallium/u_blitter: remove UTIL_BLITTER_ATTRIB_COLOR, use a constant buffer")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34291>
2025-03-31 18:42:38 +00:00
Christian Gmeiner
042138093f etnaviv: Add multi-planar YUV support
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This enables support for NV12, which are really useful when
dealing with hardware video decoders. This patch makes use
of the integrated YUV tiler to convert multi-planar to YUYV.
The binary blob uses the same method to deal with multi-planar
YUV formats. Other formarts will be added in a follow-up patch.

Tested with kmscube (nv12-1img) and the following gstreamer pipeline:

gst-launch-1.0 filesrc location=/tmp/test.mp4 ! qtdemux ! v4l2slh264dec ! video/x-raw,format=NV12 ! glimagesink

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Signed-off-by: Peter Frühberger
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3418>
2025-03-31 17:41:04 +00:00
Christian Gmeiner
58f8143da3 mesa/formats: Add MESA_FORMAT_NV12
Needed for st_pipe_format_to_mesa_format() be able to handle the NV12
format directly.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3418>
2025-03-31 17:41:04 +00:00
irql-notlessorequal
5d6b6c376f hasvk: Advertise VK_KHR_maintenance5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
b1fe67f118 hasvk: Implement VK calls and formats.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
f08c87e2b0 hasvk: Implement VkPipelineCreateFlags2KHR support
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
0d6d23a54f hasvk: Pre-plumbing needed for VK_KHR_maintenance5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
255166a349 elk: always write the VUE header
ELK equivalent of !34211, also required to avoid potential rendering errors with hasvk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
fe7e0fd4f1 elk: ensure VUE header writes in HS/DS/GS stages
ELK equivalent of !34041, required to avoid potential rendering errors with VK_KHR_maintenance5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00