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radeonsi: fix clear_depth_stencil refcnt imbalance

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After ca09c173f6, util_blitter_clear_render_target() requires
a call to util_blitter_save_fragment_constant_buffer_slot().
The radeonsi implementation was using the same sequence with
util_blitter_clear_depth_stencil() which does not need this
call. This was the cause of the refcnt imbalance.

For instance, this issue is triggered with:
"piglit/bin/ext_clear_texture-stencil -auto -fbo"
while setting GALLIUM_REFCNT_LOG=refcnt.log.

Fixes: ca09c173f6 ("gallium/u_blitter: remove UTIL_BLITTER_ATTRIB_COLOR, use a constant buffer")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34291>
This commit is contained in:
Patrick Lerda 2025-03-28 13:31:55 +01:00 • committed by Marge Bot
parent 042138093f
commit 1db8825597
1 changed files with 2 additions and 1 deletions
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3
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -14,6 +14,7 @@
enum {
SI_CLEAR = SI_SAVE_FRAGMENT_STATE | SI_SAVE_FRAGMENT_CONSTANT,
SI_CLEAR_SURFACE = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE | SI_SAVE_FRAGMENT_CONSTANT,
SI_DEPTH_STENCIL = SI_SAVE_FRAMEBUFFER | SI_SAVE_FRAGMENT_STATE,
};
void si_init_buffer_clear(struct si_clear_info *info,
@ -1430,7 +1431,7 @@ static void si_clear_depth_stencil(struct pipe_context *ctx, struct pipe_surface
return;
si_blitter_begin(sctx,
SI_CLEAR_SURFACE | (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
SI_DEPTH_STENCIL | (render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil, dstx, dsty,
width, height);
si_blitter_end(sctx);