Commit graph

103347 commits

Author SHA1 Message Date
Mauro Rossi
1a1f2b134c radv: winsys/amdgpu: include missing pthread.h header
pthread types are used in some files without explicitely including pthread.h.
This leads to compile errors on Android 7.x nougat-x86
e.g. in src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h

In file included from external/mesa/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c:31:
In file included from external/mesa/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.h:32:
external/mesa/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h:52:2: error: unknown type name 'pthread_mutex_t'
        pthread_mutex_t global_bo_list_lock;
        ^
1 error generated.

Including pthread.h explicitely solves the building error

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-07-07 20:53:59 +02:00
Karol Herbst
de13978733 nv50/ir: fix Instruction::isActionEqual for PHI instructions
phi instructions don't have the same results by simply having the same sources.
They need to be inside the same BasicBlock or share an equal condition
resulting into a path through the shader selecting equal sources as well.

short example:

cond = ...;
const0 = 0;
const1 = 1;

if (cond) {
  ssa_1 = const0;
} else {
  ssa_2 = const1;
}
ssa_3 = phi ssa_1 ssa_2;

if (!cond) {
  ssa_4 = const0;
} else {
  ssa_5 = const1;
}
ssa_6 = phi ssa_4 ssa_5;

allthough both phis actually have sources with equal results, merging them
would be wrong due to having a different condition selecting which source to
take.

For now we also stick an assert into GlobalCSE, because it should never end up
having to merge phi instructions.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-07-07 20:32:33 +02:00
Rhys Perry
f2cc694d8e nvc0/ir: use the combined tid special register
total instructions in shared programs : 5804448 -> 5804690 (0.00%)
total gprs used in shared programs    : 670065 -> 670065 (0.00%)
total shared used in shared programs  : 548832 -> 548832 (0.00%)
total local used in shared programs   : 21068 -> 21068 (0.00%)

                local     shared        gpr       inst      bytes
    helped           0           0           0           5           5
      hurt           0           0           0         191         191

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2018-07-07 20:31:56 +02:00
Jason Ekstrand
6e88561156 nir/print: Print texture and sampler indices
Commit 5fb69daa6076e56b deleted support from nir_print for printing the
texture and sampler indices on texture instructions.  This commit just
brings it back as best as we can.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-07-07 09:32:33 -07:00
Ian Romanick
f8e54d02f7 intel/compiler: Relax mixed type restriction for saturating immediates
At the time of commit 7bc6e455e2 (i965: Add support for saturating
immediates.) we thought mixed type saturates would be impossible.  We
were only thinking about type converting moves from D to F, for
example.  However, type converting moves w/saturate from F to DF are
definitely possible.  This change minimally relaxes the restriction to
allow cases that I have been able trigger via piglit tests.

Fixes new piglit tests:
 - arb_gpu_shader_fp64/execution/built-in-functions/fs-sign-sat-neg-abs.shader_test
 - arb_gpu_shader_fp64/execution/built-in-functions/vs-sign-sat-neg-abs.shader_test

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-07-06 16:20:10 -07:00
Ian Romanick
9626ea497d i965/vec4: Properly handle sign(-abs(x))
This is achived by copying the sign(abs(x)) optimization from the FS
backend.

On Gen7 an earlier platforms, this fixes new piglit tests:

 - glsl-1.10/execution/vs-sign-neg-abs.shader_test
 - glsl-1.10/execution/vs-sign-sat-neg-abs.shader_test

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-07-06 16:20:07 -07:00
Ian Romanick
88bd37c010 i965/fs: Properly handle sign(-abs(x))
Fixes new piglit tests:

 - glsl-1.10/execution/fs-sign-neg-abs.shader_test
 - glsl-1.10/execution/fs-sign-sat-neg-abs.shader_test
 - glsl-1.10/execution/vs-sign-neg-abs.shader_test
 - glsl-1.10/execution/vs-sign-sat-neg-abs.shader_test

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2018-07-06 16:20:04 -07:00
Lionel Landwerlin
c05c8d65ba vulkan: utils: handle hexadecimal values in registry
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-07-06 22:12:00 +01:00
Marek Olšák
0eaf069679 st/dri: fix a crash in server_wait_sync
Ported from i965 including the comment.

This fixes:
    dEQP-EGL.functional.reusable_sync.valid.wait_server

Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2018-07-06 16:23:37 -04:00
Mathieu Bridon
b39bdb0716 python: Stop using the Python 2 exception syntax
We could have made this compatible with Python 3 by using:

    except Exception as e:

But since none of this code actually uses the exception objects, let's
just drop them entirely.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-07-06 10:18:43 -07:00
Mathieu Bridon
e5a8d51e54 python: Use spaces, not tabs
Python 3 doesn't allow mixing spaces and tabs in a script, contrarily to
Python 2.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-07-06 10:04:55 -07:00
Mathieu Bridon
0f7b18fa0d python: Use the print function
In Python 2, `print` was a statement, but it became a function in
Python 3.

Using print functions everywhere makes the script compatible with Python
versions >= 2.6, including Python 3.

Signed-off-by: Mathieu Bridon <bochecha@daitauha.fr>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
2018-07-06 10:04:22 -07:00
Jon Turney
b3a42fa066
vma/tests: Fix compilation if limits.h defines PAGE_SIZE (v2)
per POSIX, limits.h may define PAGE_SIZE when the value is not indeterminate

v2: just change the variable name, since there's no intended correlation
here between this value and the machine's actual page size.

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2018-07-06 14:01:08 +01:00
Samuel Pitoiset
85865dbe0d radv: fix emitting the view index on GFX9
For merged shaders, VS as HS for example.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-07-06 10:22:53 +02:00
Ian Romanick
965a06dbd7 i965/vec4: Make the vec4_visitor::nir_emit_instr default case unreachable
The bug fixed by the previous commit went undetected because extra
stderr messages are not flagged by the CI.  Copy the solution from
fs_visitor::nir_emit_instr and mark the default case unreachable.

An alternate solution is to delete the default case so that the compiler
will issue a warning.  That may require more work since there are other
(impossible) cases that exist.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-07-05 21:13:32 -07:00
Ian Romanick
a4d4787327 intel/compiler: More DCE after lowering
Some of the lowering passes, nir_lower_locals_to_regs for example, can
cause some previously live code to be dead.  This pass in particular
leaves a bunch of nir_instr_type_deref instructions floating around.
This causes shader-db runs on Gen5 through Haswell to spew tons of
messages like:

    VS instruction not yet implemented by NIR->vec4

UnrealEngine4/EffectsCaveDemo/239.shader_test is one shader that
generates these messages.  Cleaning up the dead code fixes that.

To verify, I did a shader-db before and after.  Even though all the
messages are gone, the results make my brain hurt. :(

Haswell
total cycles in shared programs: 411890163 -> 411891145 (<.01%)
cycles in affected programs: 57016 -> 57998 (1.72%)
helped: 3
HURT: 11
helped stats (abs) min: 2 max: 154 x̄: 96.67 x̃: 134
helped stats (rel) min: 0.08% max: 2.23% x̄: 1.42% x̃: 1.96%
HURT stats (abs)   min: 18 max: 686 x̄: 115.64 x̃: 20
HURT stats (rel)   min: 0.81% max: 7.12% x̄: 1.87% x̃: 0.93%
95% mean confidence interval for cycles value: -51.39 191.67
95% mean confidence interval for cycles %-change: -0.14% 2.46%
Inconclusive result (value mean confidence interval includes 0).

Ivy Bridge
total cycles in shared programs: 259114802 -> 259115032 (<.01%)
cycles in affected programs: 24034 -> 24264 (0.96%)
helped: 1
HURT: 9
helped stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2
helped stats (rel) min: 0.08% max: 0.08% x̄: 0.08% x̃: 0.08%
HURT stats (abs)   min: 18 max: 48 x̄: 25.78 x̃: 20
HURT stats (rel)   min: 0.80% max: 1.94% x̄: 1.08% x̃: 0.80%
95% mean confidence interval for cycles value: 12.42 33.58
95% mean confidence interval for cycles %-change: 0.54% 1.38%
Cycles are HURT.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Fixes: 5a02ffb733 nir: Rework lower_locals_to_regs to use deref instructions
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-07-05 21:13:21 -07:00
Eric Anholt
9d0406c52f v3d: Fix leak of the default attributes BOs.
The GLES3 CTS makes a lot more progress on a run now.
2018-07-05 15:50:54 -07:00
Eric Anholt
6b11131373 v3d: Fix leak of the spill BO on context destruction. 2018-07-05 15:50:52 -07:00
Eric Anholt
4b2ba18ff3 nir: Apply fragment color clamping to gl_FragData[] as well.
From the ARB_color_buffer_float spec:

   35. Should the clamping of fragment shader output gl_FragData[n]
       be controlled by the fragment color clamp.

       RESOLVED: Since the destination of the FragData is a color
       buffer, the fragment color clamp control should apply.

Fixes arb_color_buffer_float-mrt mixed on v3d.

Reviewed-by: Rob Clark <robdclark@gmail.com>
2018-07-05 12:39:36 -07:00
Eric Anholt
03f6d26b62 v3d: Skip emitting per-RT blend state for RTs with blend disabled.
Cleans up the CL of fbo-drawbuffers2-blend a bit.  We could do better on
more complicated cases by noticing if multiple RTs have the same blend
state and emitting them in a single packet.
2018-07-05 12:39:36 -07:00
Eric Anholt
572f6ab489 v3d: Add proper support for GL_EXT_draw_buffers2's blending enables.
I had flagged it as enabled on V3D 4.x, but not actually implemented the
per-RT enables.  Fixes piglit fbo_drawbuffers2-blend.
2018-07-05 12:39:36 -07:00
Eric Anholt
5601ab3981 v3d: Add support for GL_SAMPLE_ALPHA_TO_ONE.
Fixes piglit ext_framebuffer_multisample-draw-buffers-alpha-to-one
2018-07-05 12:39:36 -07:00
Eric Anholt
7b63371420 v3d: Respect swap_color_rb for the f32_color_rb case.
We don't actually set the two flags together, but I want to use the
r/g/b/a reordered fields in the next commit.
2018-07-05 12:39:36 -07:00
Eric Anholt
dbd52585fa st/nir: Disable varying packing when doing transform feedback.
The varying packing would result in st_nir_assign_var_locations() picking
new driver_locations, despite the pipe_stream_output already being set up
for the old driver location.  This left the gallium driver with no way to
work back to what varying was referenced by pipe_stream_output.

Fixes these tests on V3D:
dEQP-GLES3.functional.transform_feedback.random.separate.points.3
dEQP-GLES3.functional.transform_feedback.random.separate.points.7
dEQP-GLES3.functional.transform_feedback.random.separate.points.9
dEQP-GLES3.functional.transform_feedback.random.separate.triangles.3
dEQP-GLES3.functional.transform_feedback.random.separate.triangles.8

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-07-05 12:38:27 -07:00
Jon Turney
ab7aa0f10c
meson: Set with_dri from with_gallium when DRI glx is explicitly configured
Set with_dri from with_gallium when DRI GLX is explicitly configured, as
well as when DRI GLX is chosen automatically.

Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2018-07-05 17:48:35 +01:00
Samuel Pitoiset
72fd93370f radv/winsys: make use of radeon_emit()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-07-05 17:23:25 +02:00
Samuel Pitoiset
f2a310849e radv: only flush CB meta in pipeline image barriers when needed
If the given image doesn't enable CMASK, FMASK or DCC that's
useless to flush CB metadata.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-07-05 17:20:16 +02:00
Samuel Pitoiset
17bb4c2cf5 radv: only flush DB meta in pipeline image barriers when needed
If the given image doesn't have HTILE, that's useless to flush
DB metadata.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-07-05 17:20:12 +02:00
Samuel Pitoiset
2a3e9c89ff radv: fix "error: initializer element is not constant" build error
GCC 4.8 fails to compile with "static const", while GCC 8.1
fails to compile with only "static".

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-05 17:12:02 +02:00
Lionel Landwerlin
78d5c1c82a util: u_queue: fix android build error
mesa/src/util/u_queue.c:242:15: error: address of array 'queue->name'
  will always evaluate to 'true' [-Werror,-Wpointer-bool-conversion]

Fixes: b238e33bc9 "kutil/queue: add a process name into a thread name"
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-05 15:42:26 +01:00
Benedikt Schemmer
93a5c9bc99 Util: fix msvc build
The MSVC preprocessor doesnt understand #warning

Fixes: 2e1e6511f7 ("util: extract get_process_name from xmlconfig.c")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-07-05 14:24:08 +01:00
Mathieu Bridon
f9b6dfd919 python: Specify the JSON separators
On Python 2, the default JSON separators are ', ' for items and ': ' for
dicts.

On Python 3, the default is the same when no indent is specified, but if
one is (and we do specify one) then the default items separator becomes
',' (the dict separator remains unchanged).

This change explicitly specifies the Python 3 default, which helps
ensuring that the output is identical, whether it was generated by
Python 2 or 3.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-05 12:52:38 +01:00
Mathieu Bridon
fe8a153648 python: Stabilize some script outputs
In Python, dictionaries and sets are unordered, and as a result their
is no guarantee that running this script twice will produce the same
output.

Using ordered dicts and explicitly sorting items makes the build more
reproducible, and will make it possible to verify that we're not
breaking anything when we move the build scripts to Python 3.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-05 12:52:12 +01:00
Lionel Landwerlin
d337713ec4 intel: tools: remove drm-uapi defines
We already embed the headers, no need to redefine defines/structs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
87915baa23 intel: intel_dump_gpu: use simulator id in captures
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
aab21cedc6 intel: devinfo: add simulator id
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Scott D Phillips
0f53948c59 intel: tools: dump-gpu: dump 48-bit addresses
For gen8+, write out PPGTT tables in aub files so that full 48-bit
addresses can be serialized.

v2: Fix handling of `end` index in map_ppgtt

v3: Correctly mark GGTT entry as present (Rafael)

Signed-off-by: Scott D Phillips <scott.d.phillips@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
6e37b949d5 intel: tools: import intel_aubdump
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
fa00b9c1c9 intel: tools: update intel_aub.h
Scott added new stuff in IGT.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
5ffa35b64d intel: batch-decoder: add missing return line
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
28476c9d81 intel: batch-decoder: don't asks for constant BO until decoding
With PPGTT mappings, our aubinator implementation can be quite slow if
we request a buffer that doesn't exist. Instead of doing a PPGTT walk
for invalid addresses (0 lengths), wait until we're sure we want to
decode the data.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Scott D Phillips
c262ec19d0 intel/batch-decoder: handle non-contiguous binding table / surface state
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-07-05 11:57:45 +01:00
Scott D Phillips
3ebee627cb intel/tools/aubinator: aubinate ppgtt aubs
v2: by Lionel
    Fix memfd_create compilation issue
    Fix pml4 address stored on 32 instead of 64bits
    Return no buffer if first ppgtt page is not mapped

v3: Drop additional memfd_create() (Rafael)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
3228335b55 intel: aubinator: handle GGTT mappings
We use memfd to store physical pages as they get read/written to and
the GGTT entries translating virtual address to physical pages.

Based on a commit by Scott Phillips.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Jason Ekstrand
2602ea89d5 util: rb-tree: A simple, invasive, red-black tree
This is a simple, invasive, liberally licensed red-black tree
implementation. It's an invasive data structure similar to the
Linux kernel linked-list where the intention is that you embed a
rb_node struct the data structure you intend to put into the
tree.

The implementation is mostly based on the one in "Introduction to
Algorithms", third edition, by Cormen, Leiserson, Rivest, and
Stein. There were a few other key design points:

 * It's an invasive data structure similar to the [Linux kernel
   linked list].

 * It uses NULL for leaves instead of a sentinel. This means a few
   algorithms differ a small bit from the ones in "Introduction to
   Algorithms".

 * All search operations are inlined so that the compiler can
   optimize away the function pointer call.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
144b40db54 intel: aubinator: drop the 1Tb GTT mapping
Now that we're softpinning the address of our BOs in anv & i965, the
addresses selected start at the top of the addressing space. This is a
problem for the current implementation of aubinator which uses only a
40bit mmapped address space.

This change keeps track of all the memory writes from the aub file and
fetch them on request by the batch decoder. As a result we can get rid
of the 1<<40 mmapped address space and only rely on the mmap aub file
\o/

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
9d08ef6335 intel: aubinator: rework register writes handling
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
86cb05a6d3 intel: aubinator: remove standard input processing option
On a follow up commit in this series, we stop copying the data from
the mmap'ed file into our big gtt mmap, and start referencing data in
it directly. So reallocating the read buffer and adding more data from
stdin wouldn't work. For that reason, let's stop supporting stdin
process.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin
08d85a8301 intel: aubinator: remove unused variables
These memory offsets are stored in the gen_batch_decode_ctx.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Mathieu Bridon
3153bcc73e gallium/auxiliary: Fix string matching
Commit f69bc797e1 did the following:

-        if format.layout in ('bptc', 'astc'):
+        if format.layout in ('astc'):

The intention was to go from matching either 'bptc' or 'astc' to
matching only 'astc'.

But the new code doesn't respect this intention any more, because in
Python `('astc')` is not a tuple containing a string, it is just the
string. (the parentheses are simply ignored)

That means we now match any substring of 'astc', for example 'a'.

This commit fixes the test to respect the original intention.

Fixes: f69bc797e1 "gallium/auxiliary: Add helper support for
                             bptc format compress/decompress"
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-05 11:48:47 +01:00