Commit graph

2166 commits

Author SHA1 Message Date
Iago Toral Quiroga
5e584a9db7 i965: skip reading unused slots at the begining of the URB for the FS
We can start reading the URB at the first offset that contains varyings
that are actually read in the URB. We still need to make sure that we
read at least one varying to honor hardware requirements.

This helps alleviate a problem introduced with 99df02ca26 for
separate shader objects: without separate shader objects we assign
locations sequentially, however, since that commit we have changed the
method for SSO so that the VUE slot assigned depends on the number of
builtin slots plus the location assigned to the varying. This fixed
layout is intended to help SSO programs by avoiding on-the-fly recompiles
when swapping out shaders, however, it also means that if a varying uses
a large location number close to the maximum allowed by the SF/FS units
(31), then the offset introduced by the number of builtin slots can push
the location outside the range and trigger an assertion.

This problem is affecting at least the following CTS tests for
enhanced layouts:

KHR-GL45.enhanced_layouts.varying_array_components
KHR-GL45.enhanced_layouts.varying_array_locations
KHR-GL45.enhanced_layouts.varying_components
KHR-GL45.enhanced_layouts.varying_locations

which use SSO and the the location layout qualifier to select such
location numbers explicitly.

This change helps these tests because for SSO we always have to include
things such as VARYING_SLOT_CLIP_DIST{0,1} even if the fragment shader is
very unlikely to read them, so by doing this we free builtin slots from
the fixed VUE layout and we avoid the tests to crash in this scenario.

Of course, this is not a proper fix, we'd still run into problems if someone
tries to use an explicit max location and read gl_ViewportIndex, gl_LayerID or
gl_CullDistancein in the FS, but that would be a much less common bug and we
can probably wait to see if anyone actually runs into that situation in a real
world scenario before making the decision that more aggresive changes are
required to support this without reverting 99df02ca26.

v2:
- Add a debug message when we skip clip distances (Ilia)
- we also need to account for this when we compute the urb setup
  for the fragment shader stage, so add a compiler util to compute
  the first slot that we need to read from the URB instead of
  replicating the logic in both places.

v3:
- Make the util more generic so it can account for all unused slots
  at the beginning of the URB, that will make it more useful (Ken).
- Drop the debug message, it was not what Ilia was asking for.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-10-02 08:27:13 +02:00
Matt Turner
3cfd6ad01c i965: Normalize types for FBL, FBH, etc
Allows the instructions to be compacted. The documentation claims that
some of these only accept UD types, even though the type doesn't change
the operation performed. Just normalize the types to ensure we get
instruction compaction.

The only functional changes are for FBL and CBIT (always use UD types)
and FBH (always use the same types).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-09-30 20:18:09 -07:00
Iago Toral Quiroga
47e527bd81 i965/fs: force pull model for 64-bit GS inputs
Triggering the push model when 64-bit inputs are involved is not easy due to
the constrains on the maximum number of registers that we allow for this mode,
however, for GS with 'points' primitive type and just a couple of double
varyings we can trigger this and it just doesn't work because the
implementation is not 64-bit aware at all. For now, let's make sure that we
don't attempt this model whith 64-bit inputs and we always fall back to pull
model for them.

Also, don't enable the VUE handles in the thread payload on the fly when we
find an input for which we need the pull model, this is not safe: if we need
to resort to the pull model we need to account for that when we setup the
thread payload so we compute the first non-payload register properly. If we
didn't do that correctly and we enable it on-the-fly here then we will end up
VUE handles on the first non-payload register which will probably lead to
GPU hangs. Instead, always enable the VUE handles for the pull model so we
can safely use them when needed. The GS is going to resort to pull model
almost in every situation anyway, so this shouldn't make a significant
difference and it makes things easier and safer.

v2: Always enable the VUE handles for pull model, this is easier and safer
    and the GS is going to fallback to pull model almost always anyway (Ken)

v3: Only clamp the URB read length if we are over the maximum reserved for
    push inputs as we were doing in the original code (Ken).

v4: No need to clamp the urb read length if invocations > 1

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-09-29 08:18:25 +02:00
Dylan Baker
a118322b4e meson: remove duplicate libisl dependency in anv
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-09-28 10:06:00 -07:00
Gwan-gyeong Mun
c951976b50 anv: add an assertion in genX(BeginCommandBuffer)
To check a valid usage requirement.

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-28 13:20:14 +01:00
Dylan Baker
d1992255bb meson: Add build Intel "anv" vulkan driver
This allows building and installing the Intel "anv" Vulkan driver using
meson and ninja, the driver has been tested against the CTS and has
seems to pass the same series of tests (they both segfault when the CTS
tries to run wayland wsi tests).

There are still a mess of TODO, XXX, and FIXME comments in here. Those
are mostly for meson bugs I'm trying to fix, or for additional things to
implement for other drivers/features.

I have configured all intermediate libraries and optional tools to not
build by default, meaning they will only be built if they're pulled in
as a dependency of a target that will actually be installed) this allows
us to avoid massive if chains, while ensuring that only the bits that
need to be built are.

v2: - enable anv, x11, and wayland by default
    - add configure option to disable valgrind
v3: - fix typo in meson_options (Nicholas)
v4: - Remove dead code (Eric)
    - Remove change to generator that was from v0 (Eric)
    - replace if chain with loop (Eric)
    - Fix typos (Eric)
    - define HAVE_DLOPEN for both libdl and builtin dl cases (Eric)
v5: - rebase on util string buffer implementation

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net> (v4)
2017-09-27 09:12:19 -07:00
Dylan Baker
848da66222 intel: use a flag instead of setting PYTHONPATH
Meson doesn't allow setting environment variables for custom targets, so
we either need to not pass this as an environment variable or use a
shell script to wrap the invocation. The chosen solution has the
advantage of working for both autotools and meson.

v2: - put rules back in top scope (Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
2017-09-27 09:07:28 -07:00
Kenneth Graunke
a553eb0fdf i965: Support copy propagating of untyped atomic surface indexes.
In the vec4 backend, SHADER_OPCODE_UNTYPED_ATOMIC's src[1] is the
surface index.  We want to copy propagate so we can use an immediate
message descriptor, rather than an indirect send.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-09-26 15:35:14 -07:00
Kenneth Graunke
66342c997f i965/vec4: Fix swizzles on atomic sources.
Atomic operation sources are scalar values, but we were failing to
select the .x component of the second operand.  For example,

   atomicCounterCompSwapARB(counter, 5u, 10u)

would generate

   mov(8) vgrf4.x:D, 5D
   mov(8) vgrf5.x:D, 10D

   mov(8) vgrf9.x:UD, vgrf4.xyzw:D
   mov(8) vgrf9.y:UD, vgrf5.xyzw:D

which wrongly selects the .y component of vgrf5, so the actual 10u value
would get dead code eliminated.  The swizzle works for the other source,
but both of them ought to be .xxxx.

Fixes the compare and swap CTS tests in:
KHR-GL45.shader_atomic_counter_ops_tests.ShaderAtomicCounterOpsExchangeTestCase

Cc: "17.2 17.1 17.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-09-26 15:35:11 -07:00
Kenneth Graunke
a62fe34098 i965/vec4: Actually handle atomic op intrinsics.
Embarassingly, someone enabled the ARB_shader_atomic_counter_ops
extension for Gen7+ but never added the intrinsics to the switch
statement in the vec4 backend, so they just hit an unreachable()
call and died.

Fixes: 40dd45d0c6 (i965: Enable ARB_shader_atomic_counter_ops)
Cc: "17.2 17.1 17.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-09-26 15:35:06 -07:00
Eric Anholt
b99cf705c8 anv: Fix some comment typos.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-26 14:50:29 -07:00
Eric Anholt
bb7c9789c2 intel/genxml: Convert a not-present-or-"1" dict to a set.
I was implementing the same enum support in broadcom's gen_pack_header.py,
and did this same simplification there.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-09-26 14:50:29 -07:00
Timothy Arceri
49e4248a93 i965/nir: export nir_optimize
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
2017-09-26 22:37:02 +10:00
Samuel Iglesias Gonsálvez
d2cd9deeb8 anv: fix viewport transformation for z component
In Vulkan, for 'z' (depth) component, the scale and translate values
for the viewport transformation are:

pz = maxDepth - minDepth
oz = minDepth

zf = pz × zd + oz

Being zd, the third component in vertex's normalized device coordinates.

Fixes: dEQP-VK.draw.inverted_depth_ranges.*

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: mesa-stable@lists.freedesktop.org
2017-09-25 06:39:40 +02:00
Anuj Phogat
f2723980b9 Revert "intel: Remove unused device info for KBL GT1.5"
This reverts commit 4c4c28ca70.

GT1.5 device info is required for few reserved pci-id's.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-09-21 14:12:19 -07:00
Kenneth Graunke
c9fbe772ba i965: Handle unwritten PSIZ/VIEWPORT/LAYER outputs in vec4 shaders.
This can occur if the shader is capturing some of the values from the
VUE header for transform feedback, but the shader hasn't written all of
them.

Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2017-09-21 09:39:27 -07:00
Topi Pohjolainen
3a1b7efce8 intel/blorp/hiz: Always set sample number
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-09-21 08:44:25 +03:00
Jason Ekstrand
d8eede1697 anv: Advertise VK_KHR_maintenance2
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
772b07d91e anv/image: Use RENDER_SURFACE_STATE::X/Y Offset on SKL+
The Broadwell method of handling uncompressed views of compressed
textures was to make the texture linear and have a tiled shadow copy.
This isn't needed on Sky Lake because the HALIGN and VALIGN parameters
are specified in surface elements and required to be a multiple of 4.
This means that we can just use the X/Y Offset fields and we can avoid
the shadow copy song and dance.  This also makes ASTC work because ASTC
can't be linear and so the shadow copy method doesn't work there.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
64f2aabcec intel/blorp: Handle clearing compressed surfaces
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
f395d0abc8 intel/blorp: Internally expose surf_convert_to_uncompressed
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
1e5fd2f839 anv/image: Support creating uncompressed views of compressed images
In order to get support everywhere, this gets a bit complicated.  On Sky
Lake and later, everything is fine because HALIGN/VALIGN are specified
in surface elements and are required to be at least 4 so any offsetting
we may need to do falls neatly within the heavy restrictions placed on
the X/Y Offset parameter of RENDER_SURFACE_STATE.  On Broadwell and
earlier, HALIGN/VALIGN are specified in pixels and are hard-coded to
align to exactly the block size of the compressed texture.  This means
that, when reinterpreted as a non-compressed texture, the tile offsets
may be anything and we can't rely on X/Y Offset.

In order to work around this issue, we fall back to linear where we can
trivially offset to whatever element we so choose.  However, since
linear texturing performance is terrible, we create a tiled shadow copy
of the image to use for texturing.  Whenever the user does a layout
transition from anything to SHADER_READ_ONLY_OPTIMAL, we use blorp to
copy the contents of the texture from the linear copy to the tiled
shadow copy.  This assumes that the client will use the image far more
for texturing than as a storage image or render target.

Even though we don't need the shadow copy on Sky Lake, we implement it
this way first to make testing easier.  Due to the hardware restriction
that ASTC must not be linear, ASTC does not work yet.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
2c8058fb68 anv: Add a new anv_surface_state struct
This struct represents a full surface state including the addresses of
the referenced main and auxiliary surfaces (if any).  This makes
relocation setup substantially simpler and allows us to move 100% of the
surface state setup logic into anv_image where it belongs.  Before, we
were manually fishing data out of surface states when emitting
relocations so we knew how to offset aux address.  It's best to keep all
of the surface state emit logic together.  This also gets us closer, at
least cosmetically, to a world of no relocations where addresses are
placed in surface states up-front.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
22e6858b2b anv/image: Break surface state fill logic into a helper
This gives us a single centralized place where we take an image view and
use it to fill out a surface state.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
c7716718ac anv/image: Add support for the VkImageViewUsageCreateInfoKHR struct
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 17:21:06 -07:00
Samuel Iglesias Gonsálvez
c71e5c30a5 anv: Advertise point clipping properties
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
29680ff9a8 anv: Add support for tessellation domain origin control
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
fc91cbe20b spirv: Flip the tessellation winding order
It's not SPIR-V that's backwards from GLSL, it's Vulkan that's backwards
from GL.  Let's make NIR consistent with the source language and do the
flipping inside the Vulkan driver instead.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
2891115671 anv/image: Add support for the new depth/stencil layouts
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 17:21:06 -07:00
Jason Ekstrand
ae8c7c703b anv/entrypoints_gen: Dedent the C code
This makes the C code be justified over to the left.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-20 14:56:45 -07:00
Józef Kucia
65a09f98ad anv: Fix descriptors copying
Trivial.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-20 13:14:49 +02:00
Jason Ekstrand
9ec51aa0fe anv: Advertise support VK_FORMAT_R8_SRGB
Unreal Engine 4 seems to really like this format for some reason.  We
don't technically have the hardware format but we do have L8_SRGB.  It's
easy enough to fake with that and a swizzle.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-19 12:06:30 -07:00
Jason Ekstrand
a8ba57d356 intel/blorp: Support clearing L8_UNORM_SRGB surfaces
Vulkan needs to be able to clear any texture you can create.  We want to
add support for VK_FORMAT_R8_SRGB and we need to use L8_UNORM_SRGB to do
that so we need to be able to clear it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-09-19 12:06:26 -07:00
Emil Velikov
2785090a2a configure.ac: split the wayland client/server confusion
At the moment wayland-clients, such as the Vulkan drivers were
over-linking against libwayland-server.so.

That went unnoticed, since both client and server code uses the
wl*interface symbols, which are present in both libwayland-client.so and
libwayland-server.so.

I've looked at correcting that, although that's orthogonal to this fix.

Note: wayland-egl does _not_ depend on wayland-client, although it does
need wayland-egl.h. There's no distinct package that provides it (I have
a WIP on the topic) so current solution will do for now.

v2: Rebase with the "...inline wayland_drm_buffer_get" patch removed.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-09-19 19:02:34 +01:00
Juan A. Suarez Romero
d3a773611c intel: automake: add isl_genX_priv.h in the source list
Fixes:

 CC       isl/isl_format_layout.lo
In file included from
../../../../src/intel/isl/isl_storage_image.c:24:0:
../../../../src/intel/isl/isl_priv.h:170:29: fatal error:
isl_genX_priv.h: No such file or directory
compilation terminated.
Makefile:2936: recipe for target 'isl/isl_storage_image.lo' failed
make[5]: *** [isl/isl_storage_image.lo] Error 1
make[5]: *** Waiting for unfinished jobs....
In file included from ../../../../src/intel/isl/isl.c:36:0:
../../../../src/intel/isl/isl_priv.h:170:29: fatal error:
isl_genX_priv.h: No such file or directory
compilation terminated.
make[5]: *** [isl/isl.lo] Error 1
Makefile:2936: recipe for target 'isl/isl.lo' failed
make[4]: *** [all] Error 2

when running `make distcheck`.

v2: Fix commit title (Emil)

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-19 19:23:46 +02:00
Chad Versace
9f763c1f9b anv/android: Disable surface and swapchain extensions (v2)
Android's Vulkan loader implements VK_KHR_surface and VK_KHR_swapchain,
and applications cannot access the driver's implementation. Moreoever,
if the driver exposes the those extension strings, then tests
dEQP-VK.api.info.instance.extensions and dEQP-VK.api.info.device fail
due to the duplicated strings.

v2: Replace !ANDROID with ANV_HAS_SURFACE. (for jekstrand)

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Tapani Pälli <tapani.palli@intel.com>
2017-09-18 14:27:27 -07:00
Chad Versace
39c9d43536 anv: Feed vk_android_native_buffer.xml to generators (v2)
Feed the XML to anv_extensions.py and anv_entrypoints_gen.py.
Do it on all platforms, not just Android. Tested on Android and Fedora.

We always parse the Android XML, regardless of target platform, to
help reduce the chance that people working on non-Android break the
Android build.

v2:
  - Squash in Tapani's changes to Android.*.mk.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
2017-09-18 14:26:54 -07:00
Chad Versace
6a5ff18039 anv: Teach generator scripts how to parse mutliple XML files
The taught scripts are anv_extensions.py and anv_entrypoints_gen.py.  To
give a script multiple XML files, call it like so:

    anv_extensions.py --xml a.xml --xml b.xml --xml c.xml ...

The scripts parse the XML files in the given order.

This will allow us to feed the scripts XML files for extensions that are
missing from the official vk.xml, such as VK_ANDROID_native_buffer.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-09-18 14:26:54 -07:00
Jason Ekstrand
400ffa748e intel/isl: Add a drm_modifier_get_default_aux_state helper
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-09-18 12:14:24 -07:00
Jason Ekstrand
1a994b053d anv: Implement VK_KHR_image_format_list
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-18 07:35:37 -07:00
Jason Ekstrand
52a89fedf2 anv: Implement VK_KHR_bind_memory2
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-09-18 07:33:59 -07:00
Kenneth Graunke
4f8d1af0f6 i965: Add an INTEL_DEBUG=reemit option.
Jason and I use this for debugging all the time.  Recompiling the driver
to enable it is kind of annoying.  It's a great thing to try along with
always_flush_batch=true and always_flush_cache=true to detect a class of
problems - namely, atoms listening to an insufficient set of dirty bits.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-09-15 21:51:45 -07:00
Kenneth Graunke
edfd8d42a9 i965: Add an INTEL_DEBUG=submit option for printing batch statistics.
When a batch is submitted, INTEL_DEBUG=bat prints a message indicating
which part of the code triggered the flush, and some statistics about
the batch/state buffer utilization.

It also decodes the batchbuffer in debug builds...which is so much
output that it drowns out the utilization messages, if that's all you
care about.

INTEL_DEBUG=submit now just does the utilization messages.
INTEL_DEBUG=bat continues to do both (as the message is a good indicator
that we're starting decode of a new batch).

v2: Rename from "flush" to "submit" (suggested by Chris) because we
    might want "flush" for PIPE_CONTROL debugging someday.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-09-13 13:52:38 -07:00
Chad Versace
5c98d3825c util: Query build-id by symbol address, not library name
This patch renames build_id_find_nhdr() to
build_id_find_nhdr_for_addr(), and changes it to never examine the
library name.

Tested on Fedora by confirming that build_id_get_data() returns the same
build-id as the file(1) tool. For BSD, I confirmed that the API used
(dladdr() and struct Dl_info) is documented in FreeBSD's manpages.

This solves two problems:

    - We can now the query the build-id without knowing the installed library's
      filename.

      This matters because Android requires specific filenames for HAL
      modules, such as "/vendor/lib/hw/vulkan.${board}.so". The HAL
      filenames do not follow the Unix convention of "libfoo.so".  In
      other words, the same query code will now work on Linux and Android.

    - Querying the build-id now works correctly when the process
      contains multiple shared objects with the same basename.
      (Admittedly, this is a highly unlikely scenario).

Cc: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-09-13 09:49:27 -07:00
Jason Ekstrand
d496780fb2 intel/eu/validate: Look up types on demand in execution_type()
We are looking up the execution type prior to checking how many sources
we have.  This leads to looking for a type for src1 on MOV instructions
which is bogus.  On BDW+, the src1 register type overlaps with the
64-bit immediate and causes us problems.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
2017-09-12 15:01:00 -07:00
Tapani Pälli
f940b1665a anv: fix build issues on release build
Fixes: d083bc1c4b ("anv: wire up vk_errorf macro to do debug reporting")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-09-12 13:29:11 +03:00
Tapani Pälli
ea314bf812 anv: remove extra 'debug:' from anv_debug_ignored_stype
anv_debug adds 'debug:' already, this is to clean following:
   debug: debug: anv_CreateDebugReportCallbackEXT: ignored VkStructureType 1000011000

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-12 09:42:19 +03:00
Tapani Pälli
a7ebb21744 anv: move brw_process_intel_debug_variable to happen early
Currently anv_perf_warn call in anv_compute_heap_size does not ever
report a perf warning. Move debug variable read as the first thing
in case there will be other perf_warn calls added.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-12 09:42:11 +03:00
Tapani Pälli
d083bc1c4b anv: wire up vk_errorf macro to do debug reporting
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-12 09:42:00 +03:00
Tapani Pälli
73638be11f anv: wire up anv_perf_warn macro to do debug reporting
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-12 09:41:10 +03:00