Also drop my email address in the copyright lines and fix some "Copyright 208
Alyssa Rosenzweig" lines, I'm not *that* old. Together this drops a lot of
boilerplate without losing any meaningful licensing information. SPDX is already
in use for the MIT-licensed code in turnip, venus, and a few other scattered
parts of the tree, so this should be ok from a Mesa licensing standpoint.
This reduces friction to create new files, by parsing the copy/paste boilerplate
and being short enough you can easily type it out if you want. It makes new
files seem less daunting: 20 lines of header for 30 lines of code is
discouraging, but 2 lines of header for 30 lines of code is reasonable for a
simple compiler pass. This has technical effects, as lowering the barrier to
making new files should encourage people to split code into more modular files
with (hopefully positive) effects on project compile time.
This helps with consistency between files. Across the tree we have at least a
half dozen variants of the MIT license text (probably more), plus code that uses
SPDX headers instead. I've already been using SPDX headers in Asahi manually, so
you can tell old vs new code based on the headers.
Finally, it means less for reviewers to scroll through adding files. Minimal
actual cognitive burden for reviewers thanks to banner blindness, but the big
headers still bloat diffs that add/delete files.
I originally proposed this in December (for much more of the tree) but someone
requested I wait until January to discuss. I've been trying to get in touch with
them since then. It is now almost April and, with still no response, I'd like to
press forward with this. So with a joint sign-off from the major authors of the
code in question, let's do this.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Emma Anholt <emma@anholt.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Rose Hudson <rose@krx.sh>
Acked-by: Lyude Paul [over IRC: "yes I'm fine with that"]
Meh'd-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22062>
Formatted loads always support vec3, so this code didn't do anything.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22117>
VMEM loads promoted from vec3 to vec4 didn't trim the vector, thus
returning vec4 on gfx6 and vec3 on later generations, which callers
don't expect.
SMEM loads were adding an extra component on gfx6, causing same issues.
Fixes: 82919e2d - amd: lower subdword UBO loads in NIR
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8693
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22117>
We implement this by emitting a draw call, which should not be registered
during occlusion query counting.
Fixes:
dEQP-VK.query_pool.occlusion_query*clear*
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22131>
The robustness buffer is used when no vertex attribute can be loaded and
robustBufferAccess is enabled.
Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21579>
As per the Vulkan spec, this is a required feature for graphics implementations.
Signed-off-by: Jarred Davies <jarred.davies@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21579>
If the primitive topology is part of the PSO, it's copied at pipeline
bind time to the dynamic state, so this checks is unnecessary.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22105>
The current implementation has a number of issues:
- it doesn't flush the depth cache, even though this can also be changed
due to fragment shader operations and thus is included in the definition
of glTextureBarrier
- it doesn't flush the vertex sampler cache
- it doesn't stall the pipeline until the flushes are done
Fix those issues and drop the comment, as it's pretty clear from the
code what is being done.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22104>
If a sampler resource is changed the vertex texture caches also need to
be flushed, as those are separate from the fragment texture caches.
It seems that some cores need the VS sampler cache flush to be in a
separate state. I have seen no adverse effects of merging the TEXTUREVS
flush into a single flush state emission on GC3000 and up, but the blob
always emits the vertex sampler cache flush as a separate state, so do
the same here to avoid nasty surprises.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22104>
Having two top-level headings in an article confuses Sphinx, and makes
both appear as separate articles in the toc-tree.
It doesn't seem like there's a good reason why the following headings
should be nested under the "Turnip"-heading anyway, so let's just make
it a sibling to the "Hardware architecture" heading.
Acked-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21948>
Sample shading can be enabled inside the fragment shader and also
per-pipeline. Separate both cases to be able to enable sample shading
by only binding a FS.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22110>
We never implemented it, and having broken mipmaps works out better
for applications and CTS. Actually implementing stencil adjust is
going to be a major pain due to stuff like the GENERAL layout.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21869>
The zap shader knows the offset of the embedded shader within the zap
sqe instructions, but uses this control reg to get it's own address in
memory, in order to calculate the address of the compute shader part of
the zap shader.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21748>
