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docs/freedreno: Fix typos

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Found by codespell

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22149>
This commit is contained in:
Harri Nieminen 2023-03-27 22:13:50 +03:00 • committed by Marge Bot
parent c9378106ed
commit eff5d950ea
2 changed files with 4 additions and 4 deletions
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6
docs/drivers/freedreno.rst
View file

@ -79,7 +79,7 @@ Hardware acronyms
Visibility Stream Compressor
PVS
Primitive Visibiliy Stream
Primitive Visibility Stream
FE
Front End? Index buffer and vertex attribute fetch cluster. Includes PC,
@ -264,7 +264,7 @@ SSBOs are just untyped buffers, but otherwise use the same descriptors and
instructions as images. Samplers use a 16byte descriptor, and UBOs use an
8byte descriptor which packs the size in the upper 15 bits of the UBO address.
In the bindless model, descriptors are split into 5 desciptor sets, which are
In the bindless model, descriptors are split into 5 descriptor sets, which are
global across shader stages (but as with bindful IBO descriptors, separate for
3d stages vs compute stage). Each hw descriptor is an array of descriptors
of configurable size (each descriptor set can be configured for a descriptor
@ -609,7 +609,7 @@ the cases where stale data is read.
stomp registers before each renderpass.
``inverse``
changes `TU_DEBUG_STALE_REGS_RANGE` meaning to
"regs that should NOT be stompted".
"regs that should NOT be stomped".
The best way to pinpoint the reg which causes a failure is to bisect the regs
range. In case when a fail is caused by combination of several registers

2
docs/drivers/freedreno/isaspec.rst
View file

@ -201,7 +201,7 @@ Overrides
In many cases, a bitset is not convenient for describing the expected
disasm syntax, and/or interpretation of some range of bits differs based
on some other field or combination of fields. These *could* be modeled
as different derived bitsets, at the expense of a combinatorical explosion
as different derived bitsets, at the expense of a combinatorial explosion
of the size of the bitset inheritance tree. For example, *every* cat2
(and cat3) instruction has both a ``(nopN)`` interpretation in addition to
the ``(rptN`)`` interpretation.