Commit graph

64939 commits

Author SHA1 Message Date
Roland Scheidegger
17eabfeccf docs: fix up status of softpipe, llvmpipe
The docs were never really up to date for them, missing just about everything.
So mark them off as all done for GL 3.3 (though softpipe is in fact quite
broken for some newer things especially wrt texturing, and both don't have
compliant, real msaa support). And add the extensions missing too (no
guarantee of completeness).

Reviewed-by: Dave Airlie <airlied@gmail.com>
2014-08-28 03:01:16 +02:00
Alexander von Gluck IV
0348429586 glsl: Add strings.h on non-MSC platforms
* IEEE Std 1003.1-2001 placed strcasecmp() in strings.h.
* ISO C99 doesn't mention strcase* in string.h
* On all platforms I could find, strcasecmp is in strings.h and string.h
  as a compatibility layer for software written pre-2001 POSIX
* Technically strcasecmp should be only in strings.h and the man
  pages back this up.
* Tested build on CentOS and Haiku

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-08-27 20:20:58 -04:00
Alex Deucher
6b48c18b03 radeon/uvd: remove comment about RV770
It doesn't seem to support field based decode after testing.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2014-08-27 10:04:13 -04:00
Christian König
80771e47b6 radeon/uvd: fix field handling on R6XX style UVD
The first UVD generation can only do frame based output.

Signed-off-by: Christian König <christian.koenig@amd.com>
2014-08-26 17:56:57 +02:00
Christian König
03a99ba9e4 vl/compositor: set the scissor before clearing the render target
Otherwise we clear areas that shouldn't be cleared.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2014-08-26 17:56:57 +02:00
Christian König
b73c20759f st/vdpau: fix vlVdpOutputSurfaceRender(Output|Bitmap)Surface
Correctly handle that the source_surface is only optional.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80561

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2014-08-26 17:56:57 +02:00
Chia-I Wu
e3c251071b ilo: use genhw command opcodes
Replace ILO_GPE_MI and ILO_GPE_CMD with magic values by descriptive genhw
macros.
2014-08-26 14:11:02 +08:00
Chia-I Wu
6c73478223 ilo: rename intel_bo_map_unsynchronized()
Rename it to intel_bo_map_gtt_async().
2014-08-26 14:10:50 +08:00
Chia-I Wu
354d84b629 ilo: remove max_batch_size
It is used to derive an artificial limit on max relocs per bo.  We choose not
to export it anymore.
2014-08-26 14:10:50 +08:00
Chia-I Wu
fbb869c1aa ilo: replace domains by reloc flags
It is simpler and is supported by the kernel.  It cannot be used with
libdrm_intel yet though.
2014-08-26 14:10:50 +08:00
Chris Forbes
01887593a4 docs: Update who is working on tessellation
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-26 07:51:11 +12:00
Chris Forbes
38a3490368 glsl: Remove bogus "OUPTUT" token
This is never used. There is another token "OUTPUT" which the lexer can
generate, though. This has been around since the dawn of time; is most
likely a typo.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-08-26 07:50:43 +12:00
Marek Olšák
83503f9e68 radeonsi: handle PIPE_BIND_BLENDABLE
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-25 13:12:24 +02:00
Marek Olšák
770719eb82 r600g: only set PIPE_BIND_BLENDABLE if colorbuffer rendering is supported
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-25 13:12:24 +02:00
Marek Olšák
bc0ae40616 r300g: handle PIPE_BIND_BLENDABLE
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-08-25 13:12:23 +02:00
Eric Anholt
7317f11859 vc4: Stop doing qpu_inst(add, NOP) or qpu_inst(NOP, mul).
Now that the extra WADDR is set, we can knock this off.  Saves a lot of
typing, and makes this code much more legible.
2014-08-24 22:13:26 -07:00
Eric Anholt
78d144f7de vc4: Set the other WADDR in the qpu instruction helpers.
Now you don't need to qpu_inst() your instruction with a NOP to get the
other waddr set.
2014-08-24 22:13:26 -07:00
Eric Anholt
54499a85ff vc4: Merge qpu_a_NOP() and qpu_m_NOP to a single qpu_NOP() helper.
Now that qpu_inst() ignores the WADDR from the other half of the
instruction, we can set both the ADD and MUL WADDRs in the NOP helper.
Thanks to that, we also no longer need to qpu_inst(NOP, NOP).
2014-08-24 22:13:25 -07:00
Eric Anholt
1a7035f386 vc4: Ignore WADDRs from the other half of the instruction when merging.
This allows setting the opposite-side WADDR to NOP (a non-zero value) in
qpu_* helpers, so that we don't need to qpu_inst() merge them with NOPs
all the time just to get the waddr set.
2014-08-24 22:13:25 -07:00
Eric Anholt
3212bafc28 vc4: Fix LT/GE set-0-or-1 compares.
We were using the integer sub, which worked for the common case of EQ and
NE.  Fixes fs-lessThan-ivec2-ivec2 and other tests.
2014-08-24 22:13:25 -07:00
Eric Anholt
e2f66315cb u_vbuf: Add a few more format fallbacks.
Fixes piglit draw-vertices and gl-2.0-vertexattribpointer on vc4, where
I'm only advertising R32F to RGBA32F support so far.

Note: regresses gl-1.5-normal3b3s-invariance due to introduced flushes and
missing depth buffer load/store support in the driver.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-24 22:13:25 -07:00
Eric Anholt
bbbe3b65ad u_vbuf: Simplify the format fallback translation.
Individual caps made supporting new fallbacks more complicated than it
needed to be.  Instead, just make a table of fallbacks at context init
time.

v2: Fix inverted "do we need to install vbuf?" flagging caught by Marek.

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
2014-08-24 22:13:25 -07:00
Rob Clark
306e421887 freedreno/a2xx: fix segfault
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-08-24 13:09:47 -04:00
Rob Clark
bd3b096467 freedreno/a3xx: handle first/last level properly
Fixes some assumptions about first_level being zero.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-08-24 13:09:23 -04:00
Rob Clark
b40a6c2b17 freedreno: implement pipe_flush_resource()
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-08-24 13:09:00 -04:00
Rob Clark
478a08ebd2 freedreno: don't ignore src/dst level
Don't ignore src/dst_level in pipe_copy_region.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-08-24 13:08:14 -04:00
Eric Anholt
8d8a5eb792 vc4: Fix save/restore of the VS/FS in the blitter.
When I made the shader cache take the .fs member and moved the binding
point to .bind_fs, I failed to update these.  Fixes crashes in
copyteximage-related tests.
2014-08-23 16:30:42 -07:00
Eric Anholt
9542e68207 vc4: Clear padding of ioctl arguments.
Fixes valgrind complaints from valgrind being unaware of our ioctls.
2014-08-23 16:30:34 -07:00
Vinson Lee
c2867f5b36 auxilary/os: Add Solaris support in os_get_total_physical_memory.
The patch fixes the build on Oracle Solaris.

  CC     os/os_misc.lo
"os/os_misc.c", line 59: #error: unexpected platform in os_sysinfo.c

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-08-22 18:24:34 -07:00
Alexander von Gluck IV
12a679a6f6 gallium/targets: Haiku, Fix some improper type warnings 2014-08-22 19:37:19 -04:00
Alexander von Gluck IV
31406d978d gallium/targets: Clean up Haiku softpipe renderer visual
* Drop creating gl_config first as it's only really used
  to create the state tracker visual.
2014-08-22 19:37:19 -04:00
Carl Worth
23163df24c glcpp: Don't use alternation in the lookahead for empty pragmas.
We've found that there's a buffer overrun bug in flex that's triggered by
using alternation in a lookahead pattern.

Fortunately, we don't need to match the exact {NEWLINE} expression to
detect an empty pragma. It suffices to verify that there are no non-space
characters before any newline character. So we can use a simple [\r\n] to
get the desired behavior while avoiding the flex bug.

Fixes the regression of piglit's 17000-consecutive-chars-identifier test,
(which has been crashing since commit
04e40fd337 ).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82472
Signed-off-by: Carl Worth <cworth@cworth.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

CC: <mesa-stable@lists.freedesktop.org>
2014-08-22 15:14:59 -07:00
Kenneth Graunke
97d03b9366 i965: Disable try_emit_b2f_of_compare on Gen4-6.
The optimization relies on CMP setting the destination to 0, which is
equivalent to 0.0f.  However, early platforms only set the least
significant byte, leaving the other bits undefined.  So, we must disable
the optimization on those platforms.

Oddly, Sandybridge wasn't reported as broken.  The PRM states that it
only sets the LSB, but the internal documentation says that it follows
the IVB behavior.  Since it wasn't reported as broken, we believe it
really does follow the IVB behavior.

v2: Allow the optimization on Sandybridge (requested by Matt).

+32 piglits on Ironlake.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?=79963
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-08-22 11:40:32 -07:00
Matt Turner
b8aa1005c8 i965/fs: Preserve CFG in predicated break pass.
Operating on this code,

B0: ...
    cmp.ne.f0(8)
    (+f0) if(8)
B1: break(8)
B2: endif(8)

We can delete B2 without attempting to merge any blocks, since the
break/continue instruction necessarily ends the previous block.

After deleting the if instruction, we attempt to merge blocks B0 and B1.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
3c4c2a6e30 i965/fs: Rename variable in predicated break pass.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
1db74a423f i965/fs: Preserve CFG in the SEL peephole.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
81755bc67b i965: Preserve CFG when deleting dead control flow.
This pass deletes an IF/ELSE/ENDIF or IF/ENDIF sequence, or the ELSE in
an ELSE/ENDIF sequence.

In the typical case (where IF and ENDIF) aren't the only instructions in
their basic blocks, we can simply remove the instructions (implicitly
deleting the block containing only the ELSE), and attempt to merge
blocks B0 and B2 together.

B0: ...
    (+f0) if(8)
B1: else(8)
B2: endif(8)
    ...

If the IF or ENDIF instructions are the only instructions in their
respective basic blocks (which are deleted by the removal of the
instructions), we'll want to instead merge the next blocks.

Both B0 and B2 are possibly removed by the removal of if & endif.
Same situation for if/endif. E.g., in the following example we'd remove
blocks B1 and B2, and then attempt to combine B0 and B3.

B0: ...
B1: (+f0) if(8)
B2: endif(8)
B3: ...

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
9cf06e27e1 i965/cfg: Add functions to combine basic blocks.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
5e6ead5e8b i965/cfg: Point to bblock_t containing associated control flow
... rather than pointing directly to the associated instruction. This
will let us set the block containing the IF statement's else-pointer to
NULL, when we delete a useless ELSE instruction, as in the case

   (+f0) if(8)
   ...
   else(8)
   endif(8)

Also, remove the pointer to the ENDIF, since it's unused, and it was
also potentially wrong, in the case of a basic block containing both an
ENDIF and an IF instruction:

   endif(8)
   cmp.ne.f0(8) ...
   (+f0) if(8)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
2a98ebd42b i965/fs: Preserve CFG in register allocation.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
20a849b4aa i965: Use basic-block aware insertion/removal functions.
To avoid invalidating and recreating the control flow graph. Also stop
invalidating the CFG in places we didn't add or remove an instruction.

cfg calculations:     202951 -> 80307 (-60.43%)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
e0aa45768c i965: Add invalidate_cfg parameter to invalidate_live_intervals().
Will let us avoid invalidating the CFG if the optimization pass has
removed instructions using the new basic block methods.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
3d6d4dc6f7 i965: Add basic-block aware backend_instruction::insert_* methods.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:34 -07:00
Matt Turner
dc527fbf7d i965: Add a basic-block aware backend_instruction::remove method.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:33 -07:00
Matt Turner
240adc1346 i965/cfg: Add a function to remove a block from the cfg.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:33 -07:00
Matt Turner
b7d50beea4 i965/cfg: Add functions to test if a block is a successor/predecessor.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2014-08-22 10:23:33 -07:00
Eric Anholt
e51e20c35e vc4: Add support for fragment discards.
Fixes piglit glsl-fs-discard-01 and -03, and allows a lot of mesa demos to
start running.  glsl-fs-discard-02 has a problem where the first tile is
not getting stored on the first render.
2014-08-22 10:16:58 -07:00
Eric Anholt
0f894b2795 vc4: Make some helpers for setting condition codes in instructions. 2014-08-22 10:16:58 -07:00
Eric Anholt
cc68be2620 vc4: Avoid using undefined values when there's no color write.
The simulator assertion fails when you read-before-write a temporary
value, and there's no point in doing the packing if there was no color
written.
2014-08-22 10:16:58 -07:00
Eric Anholt
ae83955b1d vc4: Emit the scoreboard wait just when it's needed.
This should improve performance on real hardware by allowing more shader
instances to run in parallel.  It also fixes assertion failures in tests
that don't emit a fragment color, since otherwise we didn't have enough
instructions to fit our signals in.
2014-08-22 10:16:58 -07:00