Commit graph

221099 commits

Author SHA1 Message Date
Samuel Pitoiset
0f2f9a9045 radv/nir: adjust lowering of immediate samplers for descriptor heap
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:25 +00:00
Samuel Pitoiset
a44303ff11 radv/nir: adjust lowering of ycbcr tex instructions for descriptor heap
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:25 +00:00
Samuel Pitoiset
54e2a1d2e4 radv: call vk_nir_lower_descriptor_heaps()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:24 +00:00
Samuel Pitoiset
eac2c1f141 radv: keep track of descriptor heap mapping in the shader layout
This will be used by the common lowering.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:24 +00:00
Samuel Pitoiset
cebac5a427 radv/rt: declare shader arguments for resource/sampler heaps
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:24 +00:00
Samuel Pitoiset
cdfb9a24ba radv: declare shader arguments for resource/sampler heaps
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:23 +00:00
Samuel Pitoiset
b29743f91c radv: add shader info about whether descriptor heap is used
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:23 +00:00
Samuel Pitoiset
62629d3e3c radv: use 32-bit memory types for descriptor heap buffers
Descriptors must be allocated in the 32-bit addr space.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:23 +00:00
Samuel Pitoiset
e81c375b4a radv: make radv_make_sampler_descriptor() non-static
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:23 +00:00
Samuel Pitoiset
1f15a71afe radv: add support for custom border colors with descriptor heap
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:23 +00:00
Samuel Pitoiset
8da71ae5a2 radv: add a new helper to make a sampler descriptor
For future work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:22 +00:00
Samuel Pitoiset
afd736bfd7 radv: zero-allocate graphics shader stages
This can prevent issues with unitialized memory. RT and compute
stages are already zero-initialized.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:22 +00:00
Samuel Pitoiset
0b016f4bff nir: add new system values for descriptor heap RT traversal inputs
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39483>
2026-04-14 10:10:22 +00:00
Erik Faye-Lund
dc4efab205 pan/ci: update expectations
These are based on nightlies. It's unclear if one of the t760 flakes
should really be a fail or a flake, but I have another MR that tries to
clean up the flakes pending; I'll address that there, as there's other
related flakes that probably should change as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40943>
2026-04-14 08:51:52 +00:00
Lars-Ivar Hesselberg Simonsen
a23cebcd60 panfrost: Add support for 64 bit gpu_id
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Update the gallium driver's use of gpu_id to support 64 bit gpu_ids.

Reviewed-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40921>
2026-04-14 10:12:25 +02:00
Lars-Ivar Hesselberg Simonsen
fd3aafabe9 pan/model: Expose prod_id and rev functions
Some code in gallium was making assumptions of how the gpu_id is laid
out, which will not work for 64 bit gpu_ids.

Expose pan_prod_id and pan_rev from the model to collect this logic in a
single place.

Reviewed-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40921>
2026-04-14 10:12:00 +02:00
Erik Faye-Lund
739e3d20f0 docs/panfrost: fix heading-levels
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These headings shouldn't all be on the same level; the first one is the
heading for the article, but the subsequent ones should be subheadings.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40933>
2026-04-14 05:39:23 +00:00
Tapani Pälli
745dc66b69 anv: fix Wa_14024015672 interaction in blorp
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This was causing issue within hiz clears, apply workaround only
when doing RT writes (not for WM_HZ ops).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/14533
Fixes: 7be8af1dad ("anv: deal with Wa 14024015672 on the blorp path")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40913>
2026-04-14 03:15:14 +00:00
Karol Herbst
f3ce8fe90b nak: properly copy prop neg/abs float sources for flushed values
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This allows us to copy prop fadd.ftz -rZ, -|ssa| into consuming
instructions giving us nice gains across the board.

Totals from 1033868 (85.24% of 1212873) affected shaders:
CodeSize: 8813536528 -> 8355226128 (-5.20%); split: -5.21%, +0.01%
Number of GPRs: 44954066 -> 44299483 (-1.46%); split: -1.52%, +0.06%
SLM Size: 799688 -> 798544 (-0.14%)
Static cycle count: 4646939330 -> 4485129185 (-3.48%); split: -3.67%, +0.18%
Spills to memory: 35405 -> 33136 (-6.41%); split: -6.41%, +0.01%
Fills from memory: 35405 -> 33136 (-6.41%); split: -6.41%, +0.01%
Spills to reg: 196547 -> 196231 (-0.16%); split: -1.22%, +1.06%
Fills from reg: 201227 -> 200988 (-0.12%); split: -1.00%, +0.88%
Max warps/SM: 44143984 -> 44306960 (+0.37%); split: +0.38%, -0.01%

Reviewed-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40897>
2026-04-13 23:15:10 +00:00
Karol Herbst
8170f18d9b nak/copy_prop: allow modified F16v2 and F16 sources
Seems to help a couple of shaders using MUFU.F16

Totals from 178 (0.01% of 1212873) affected shaders:
CodeSize: 5929856 -> 5925088 (-0.08%); split: -0.08%, +0.00%
Static cycle count: 8667151 -> 8665940 (-0.01%); split: -0.02%, +0.00%

Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40897>
2026-04-13 23:15:10 +00:00
Rhys Perry
a6b86d43d3 ir3/ra: fix copy-paste error
I don't entirely understand what this is all doing, but this looks like a
copy-paste error.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 26.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40480>
2026-04-13 22:28:15 +00:00
Rhys Perry
54af9431d1 ir3/array_to_ssa: initialize ir3_instruction::data
This should have already been NULL because this looks like the first time
this field is used, but that's a bit fragile.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40480>
2026-04-13 22:28:15 +00:00
Rhys Perry
4f0fb5784f ir3/array_to_ssa: skip remove_trivial_phi for non-array phis
remove_trivial_phi() mostly does nothing for non-array phis, but it
rewrites sources if their definining instruction are trivial phis.

In the case of trivial phis in the loop continue block (for loops with
divergent non-trivial continues), we might need to keep those if they
write a shared register, because the source of the trivial phi will not be
reachable from the loop header phi.

In this example, the predecessors of the continue block should be block2,
but the physical predecessors are block2 and block3, requiring a phi in
the continue block which will then be lowered by ir3_lower_shared_phis.
loop {
   block1:
   a = phi 0, b
   if (divergent) {
      block2:
      b = a + 1
      continue;
   }
   block3:
   break;
}

Fixes RA validation error when compiling blackmythwukong/5645a84e669a6179
from radv_fossils.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Backport-to: 26.0
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40480>
2026-04-13 22:28:15 +00:00
Mary Guillemard
3be57aa4c3 nak: Allows predicate in legalize_ext_instr
With OpLd now having a predicate, we forgot to update legalize_ext_instr
to allow predicates for it.

We should really get ride of those functions but for now let's keep it
simple and sync the implementation to what SM20 backend have.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Fixes: 9d90cbc314 ("nak: add input predicate to load_global_nv and OpLd")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40934>
2026-04-13 22:13:06 +00:00
Pohsiang (John) Hsu
0f56fd0120 mediafoundation: remove published codecapi
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40895>
2026-04-13 21:58:43 +00:00
Pohsiang (John) Hsu
2af4938328 mediafoundation: add support for GPU priority setting via IMFDXGIScheduler
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40895>
2026-04-13 21:58:43 +00:00
Michael Cheng
06c9c08c48 intel/ds: report when OA metrics are unavailable
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Promote DBG() failure paths in enumerate_sysfs_metrics() to mesa_logw()
so users see why OA metrics are unavailable without needing INTEL_DEBUG.
Also log in PPS when no OA queries are available after initialization.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40898>
2026-04-13 21:31:51 +00:00
Michael Cheng
16c17d6698 intel/ds: report when OA metric access is blocked by kernel policy
When observation_paranoid (xe) or perf_stream_paranoid (i915) prevents
unprivileged access to OA metrics, the existing code silently returns no
OA queries. PPS then fails with just a segfault.

This patch adds INTEL_PERF_FEATURE_OA_BLOCKED_BY_POLICY to
intel_perf_features, set by both KMD backends when the paranoid sysctl
exists but lacks sufficent privilage. PPS checks this flag immediately
after initialising intel_perf and returns an error before  attempting
metric-set selection.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40898>
2026-04-13 21:31:51 +00:00
Samuel Pitoiset
1950b6c1a7 vulkan: mark RP attachments as invalid when no rendering create info
VkPipelineRenderingCreateInfo is only required in the fragment output
interface lib. For pre-rasterization shaders and fragment shader state
libs, only the view mask is used but it's optional.

If the attachments info isn't marked invalid merging renderpass info
during lib imports wouldn't work because it would assume that the first
lib has attachment info (eg. the pre-rasterization lib).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15241
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40870>
2026-04-13 21:01:43 +00:00
Lionel Landwerlin
4dfedcca45 elk: don't support frontfacing ternary optimization on != 32bit
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40931>
2026-04-13 20:32:06 +00:00
Lionel Landwerlin
a84c12414c brw: don't support frontfacing ternary optimization on != 32bit
Fix shader compilation on Crimson Desert :

  16    %1995 = b32csel %1992, %1993, %1994

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40931>
2026-04-13 20:32:06 +00:00
Nanley Chery
b50bb53630 intel/blorp: Fix width scaling for YCBCR copies
Fixes: eb8883f3ef ("intel/blorp: Redescribe surfaces for copies")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15267
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40930>
2026-04-13 20:03:41 +00:00
Job Noorman
4e456ebde4 ir3/collect_info: remove max_const calculation
constlen is now directly calculated from the const allocations; no need
to infer it from const reg usage anymore.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40929>
2026-04-13 19:15:59 +00:00
Job Noorman
c7e7d68912 ir3: remove unused ir3_context::has_relative_load_const_ir3
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40929>
2026-04-13 19:15:59 +00:00
Job Noorman
86f3c0c4c2 ir3: simplify constlen calculation
Instead of inferring constlen from the usage of const registers by
various instructions, we can calculate it directly from the const file
allocations. This greatly simplifies the calculation of constlen.

Note that the increase in constlen comes from a few binning variants.
This doesn't matter as the constlen of the corresponding non-binning
variant is used for those anyway.

Totals from 73 (0.04% of 176258) affected shaders:
Constlen: 3428 -> 3720 (+8.52%)

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40929>
2026-04-13 19:15:59 +00:00
Mary Guillemard
59d9bc7bee hk: Add HK_MAX_RTS to maxFragmentCombinedOutputResources
Some checks are pending
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The spec also mentions "output Location decorated color attachments".

Signed-off-by: Mary Guillemard <mary@mary.zone>
Fixes: 564b061981 ("hk: Increase maxFragmentCombinedOutputResources to HK_MAX_DESCRIPTORS")
Reviewed-by: Janne Grunau <j@jannau.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40925>
2026-04-13 19:02:08 +00:00
Mary Guillemard
13f98d8658 nvk: Adjust maxFragmentCombinedOutputResources to match max descriptors limit
This was set to the lowest allowed value by spec but it should really be
matching the max descriptors limit.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15249 for NVK
Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40868>
2026-04-13 18:44:08 +00:00
Mary Guillemard
ad35eb6297 bin: Add Tested-by in rb.py
We already have a nice script, let's add the only missing option here.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40932>
2026-04-13 18:01:16 +00:00
Job Noorman
3a076beb13 ir3/analyze_ubo_ranges: don't over-align consts when loaded via preamble
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Consts don't need to be const_upload_unit aligned when initialized in
the preamble.

Totals from 121136 (68.73% of 176258) affected shaders:
MaxWaves: 1731152 -> 1731238 (+0.00%); split: +0.01%, -0.01%
Instrs: 41003924 -> 41006922 (+0.01%); split: -0.04%, +0.04%
CodeSize: 83451224 -> 84153136 (+0.84%); split: -0.15%, +0.99%
NOPs: 6920243 -> 6923031 (+0.04%); split: -0.20%, +0.24%
MOVs: 1202942 -> 1203260 (+0.03%); split: -0.13%, +0.16%
COVs: 654863 -> 654827 (-0.01%); split: -0.01%, +0.00%
Full: 1356271 -> 1356003 (-0.02%); split: -0.03%, +0.01%
(ss): 1019993 -> 1019657 (-0.03%); split: -0.16%, +0.12%
(sy): 489430 -> 489607 (+0.04%); split: -0.07%, +0.10%
(ss)-stall: 3878805 -> 3875997 (-0.07%); split: -0.21%, +0.13%
(sy)-stall: 14655425 -> 14660516 (+0.03%); split: -0.08%, +0.11%
STPs: 9680 -> 9653 (-0.28%)
LDPs: 17026 -> 16999 (-0.16%)
Preamble Instrs: 8805343 -> 9195550 (+4.43%); split: -1.65%, +6.08%
Early Preamble: 101798 -> 103143 (+1.32%); split: +1.44%, -0.12%
Constlen: 5761784 -> 4356540 (-24.39%); split: -24.40%, +0.02%
Subgroup size: 832 -> 1664 (+100.00%)
Cat0: 7631222 -> 7634040 (+0.04%); split: -0.18%, +0.22%
Cat1: 1897357 -> 1897579 (+0.01%); split: -0.09%, +0.10%
Cat2: 15537632 -> 15537426 (-0.00%); split: -0.00%, +0.00%
Cat6: 424903 -> 424996 (+0.02%); split: -0.00%, +0.02%
Cat7: 1002957 -> 1003028 (+0.01%); split: -0.07%, +0.08%

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40908>
2026-04-13 15:38:31 +00:00
Job Noorman
f2d4529494 ir3/analyze_ubo_ranges: add const_align_vec4 helper
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40908>
2026-04-13 15:38:31 +00:00
Mike Blumenkrantz
4b3bd6b0b5 vulkan/runtime: handle null pCounterBuffers with xfb binds
Some checks are pending
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this is legal

cc: mesa-stable

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40892>
2026-04-13 14:59:55 +00:00
Mike Blumenkrantz
9ff879441f radv: handle null pCounterBuffers with xfb binds
this is legal

cc: mesa-stable

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40892>
2026-04-13 14:59:55 +00:00
Mike Blumenkrantz
ab6cdd64c1 lavapipe: VK_EXT_primitive_restart_index
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40783>
2026-04-13 10:40:17 -04:00
Mike Blumenkrantz
88fd02daae lavapipe: update prim restart index on index buffer bind
this makes more sense functionally, as the restart index only changes
when the index size changes (and is harmless to update even if restart
isn't enabled)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40783>
2026-04-13 10:39:46 -04:00
Lionel Landwerlin
0927de4631 anv: enable storageInputOutput16
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40821>
2026-04-13 14:01:04 +00:00
Lionel Landwerlin
46d42b63da brw: add support for < 32bit io values
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40821>
2026-04-13 14:01:04 +00:00
Juan A. Suarez Romero
41fecb5253 broadcom/ci: update expected results
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Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40927>
2026-04-13 12:48:28 +00:00
Jesse Natalie
2c99dc8a18 d3d12: Don't allow CPU storage for huge buffers
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40896>
2026-04-13 12:33:20 +00:00
Danylo Piliaiev
889f71f71a tu: Add tracepoints for clear/copy/blit/lrz ops
There shouldn't be many per frame, so it won't be spammy.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40788>
2026-04-13 11:29:48 +00:00
Georg Lehmann
8d52c3840b radv: do not remove point size variable
This is now done later on lowered io.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40907>
2026-04-13 10:58:01 +00:00