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pan/model: Expose prod_id and rev functions

Browse source 
Some code in gallium was making assumptions of how the gpu_id is laid
out, which will not work for 64 bit gpu_ids.

Expose pan_prod_id and pan_rev from the model to collect this logic in a
single place.

Reviewed-by: Marc Alcala Prieto <marc.alcalaprieto@arm.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40921>
This commit is contained in:
Lars-Ivar Hesselberg Simonsen 2026-04-13 10:37:41 +02:00
parent 739e3d20f0
commit fd3aafabe9
5 changed files with 53 additions and 48 deletions
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4
src/gallium/drivers/panfrost/pan_device.h
View file

@ -176,13 +176,13 @@ panfrost_device_gpu_id(const struct panfrost_device *dev)
static inline uint32_t
panfrost_device_gpu_prod_id(const struct panfrost_device *dev)
{
return dev->kmod.dev->props.gpu_id >> 16;
return pan_prod_id(dev->kmod.dev->props.gpu_id);
}
static inline uint32_t
panfrost_device_gpu_rev(const struct panfrost_device *dev)
{
return dev->kmod.dev->props.gpu_id & BITFIELD_MASK(16);
return pan_rev(dev->kmod.dev->props.gpu_id);
}
static inline int

2
src/gallium/drivers/panfrost/pan_screen.c
View file

@ -140,7 +140,7 @@ get_max_msaa(struct panfrost_device *dev, enum pipe_format format)
* the r1p0 version, which prevents 16x MSAA from working properly.
*/
if (panfrost_device_gpu_prod_id(dev) == 0x750 &&
panfrost_device_gpu_rev(dev) < 0x1000)
panfrost_device_gpu_rev(dev) < PAN_REV(1, 0))
max_msaa = MIN2(max_msaa, 8);
if (dev->model->quirks.max_4x_msaa)

2
src/panfrost/compiler/midgard/midgard_quirks.h
View file

@ -57,7 +57,7 @@
static inline unsigned
midgard_get_quirks(uint64_t gpu_id)
{
switch (MIDGARD_PRODUCT_ID(gpu_id)) {
switch (pan_prod_id(gpu_id)) {
case 0x600:
return MIDGARD_OLD_BLEND | MIDGARD_BROKEN_BLEND_LOADS |
MIDGARD_BROKEN_LOD | MIDGARD_NO_UPPER_ALU | MIDGARD_NO_OOO |

62
src/panfrost/model/pan_model.c
View file

@ -6,14 +6,11 @@
#include "pan_model.h"
/* GPU revision (rXpY) */
#define GPU_REV(X, Y) (((X) & 0xf) << 12 | ((Y) & 0xff) << 4)
/* Fixed "minimum revisions" */
#define GPU_REV_NONE (~0)
#define GPU_REV_ALL GPU_REV(0, 0)
#define GPU_REV_R0P3 GPU_REV(0, 3)
#define GPU_REV_R1P1 GPU_REV(1, 1)
#define GPU_REV_ALL PAN_REV(0, 0)
#define GPU_REV_R0P3 PAN_REV(0, 3)
#define GPU_REV_R1P1 PAN_REV(1, 1)
#define MODEL(gpu_prod_id_, gpu_variant_, shortname, counters, ...) \
{ \
@ -27,11 +24,6 @@
#define MIDGARD_MODEL(gpu_prod_id, shortname, counters, ...) \
MODEL(gpu_prod_id, 0, shortname, counters, ##__VA_ARGS__)
/* Assume 8 bits per field. This ensures the prod_id is always greater than
* Midgard's. */
#define PROD_ID(arch_major, arch_minor, prod_major) \
(((arch_major) << 16) | ((arch_minor) << 8) | (prod_major))
#define BIFROST_MODEL(gpu_prod_id, shortname, counters, ...) \
MODEL(gpu_prod_id, 0, shortname, counters, ##__VA_ARGS__)
@ -74,34 +66,34 @@ const struct pan_model pan_model_list[] = {
MIDGARD_MODEL(0x860, "T860", "T86x", MODEL_ANISO(NONE), MODEL_TB_SIZES( 8192, 8192)),
MIDGARD_MODEL(0x880, "T880", "T88x", MODEL_ANISO(NONE), MODEL_TB_SIZES( 8192, 8192)),
BIFROST_MODEL(PROD_ID(6, 0, 0), "G71", "TMIx", MODEL_ANISO(NONE), MODEL_TB_SIZES( 4096, 4096)),
BIFROST_MODEL(PROD_ID(6, 2, 1), "G72", "THEx", MODEL_ANISO(R0P3), MODEL_TB_SIZES( 8192, 4096)),
BIFROST_MODEL(PROD_ID(7, 0, 0), "G51", "TSIx", MODEL_ANISO(R1P1), MODEL_TB_SIZES( 8192, 8192)),
BIFROST_MODEL(PROD_ID(7, 0, 3), "G31", "TDVx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)),
BIFROST_MODEL(PROD_ID(7, 2, 1), "G76", "TNOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)),
BIFROST_MODEL(PROD_ID(7, 2, 2), "G52", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)),
BIFROST_MODEL(PROD_ID(7, 4, 2), "G52 r1", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)),
BIFROST_MODEL(PAN_PROD_ID(6, 0, 0), "G71", "TMIx", MODEL_ANISO(NONE), MODEL_TB_SIZES( 4096, 4096)),
BIFROST_MODEL(PAN_PROD_ID(6, 2, 1), "G72", "THEx", MODEL_ANISO(R0P3), MODEL_TB_SIZES( 8192, 4096)),
BIFROST_MODEL(PAN_PROD_ID(7, 0, 0), "G51", "TSIx", MODEL_ANISO(R1P1), MODEL_TB_SIZES( 8192, 8192)),
BIFROST_MODEL(PAN_PROD_ID(7, 0, 3), "G31", "TDVx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)),
BIFROST_MODEL(PAN_PROD_ID(7, 2, 1), "G76", "TNOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)),
BIFROST_MODEL(PAN_PROD_ID(7, 2, 2), "G52", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192)),
BIFROST_MODEL(PAN_PROD_ID(7, 4, 2), "G52 r1", "TGOx", MODEL_ANISO(ALL), MODEL_TB_SIZES( 8192, 8192)),
VALHALL_MODEL(PROD_ID(9, 0, 1), 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
VALHALL_MODEL(PAN_PROD_ID(9, 0, 1), 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
MODEL_RATES(2, 4, 32)),
VALHALL_MODEL(PROD_ID(9, 0, 3), 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
VALHALL_MODEL(PAN_PROD_ID(9, 0, 3), 0, "G57", "TNAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
MODEL_RATES(2, 4, 32)),
VALHALL_MODEL(PROD_ID(10, 8, 7), 0, "G610", "TVIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
VALHALL_MODEL(PAN_PROD_ID(10, 8, 7), 0, "G610", "TVIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
MODEL_RATES(4, 8, 64)),
VALHALL_MODEL(PROD_ID(10, 12, 4), 0, "G310v1", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
VALHALL_MODEL(PAN_PROD_ID(10, 12, 4), 0, "G310v1", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
MODEL_RATES(2, 2, 16)),
VALHALL_MODEL(PROD_ID(10, 12, 4), 1, "G310v2", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
VALHALL_MODEL(PAN_PROD_ID(10, 12, 4), 1, "G310v2", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
MODEL_RATES(2, 4, 32)),
VALHALL_MODEL(PROD_ID(10, 12, 4), 2, "G310v3", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
VALHALL_MODEL(PAN_PROD_ID(10, 12, 4), 2, "G310v3", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(16384, 8192),
MODEL_RATES(4, 4, 48)),
VALHALL_MODEL(PROD_ID(10, 12, 4), 3, "G310v4", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
VALHALL_MODEL(PAN_PROD_ID(10, 12, 4), 3, "G310v4", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
MODEL_RATES(4, 8, 48)),
VALHALL_MODEL(PROD_ID(10, 12, 4), 4, "G310v5", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
VALHALL_MODEL(PAN_PROD_ID(10, 12, 4), 4, "G310v5", "TVAx", MODEL_ANISO(ALL), MODEL_TB_SIZES(32768, 16384),
MODEL_RATES(4, 8, 64)),
FIFTHGEN_MODEL(PROD_ID(12, 8, 0), 4, "G720", "TTIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 32768),
FIFTHGEN_MODEL(PAN_PROD_ID(12, 8, 0), 4, "G720", "TTIx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 32768),
MODEL_RATES(4, 8, 128)),
FIFTHGEN_MODEL(PROD_ID(13, 8, 0), 4, "G725", "TKRx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 65536),
FIFTHGEN_MODEL(PAN_PROD_ID(13, 8, 0), 4, "G725", "TKRx", MODEL_ANISO(ALL), MODEL_TB_SIZES(65536, 65536),
MODEL_RATES(4, 8, 128)),
};
/* clang-format on */
@ -123,18 +115,6 @@ const struct pan_model pan_model_list[] = {
#undef MODEL_RATES
#undef MODEL_QUIRKS
static uint32_t
get_prod_id(uint64_t gpu_id)
{
unsigned arch = pan_arch(gpu_id);
if (arch < 6)
return MIDGARD_PRODUCT_ID(gpu_id);
return PROD_ID(PAN_ARCH_MAJOR(gpu_id), PAN_ARCH_MINOR(gpu_id),
PAN_PRODUCT_MAJOR(gpu_id));
}
#undef PROD_ID
/*
* Look up a supported model by its GPU ID, or return NULL if the model is not
* supported at this time.
@ -142,7 +122,7 @@ get_prod_id(uint64_t gpu_id)
const struct pan_model *
pan_get_model(uint64_t gpu_id, uint32_t gpu_variant)
{
uint32_t gpu_prod_id = get_prod_id(gpu_id);
uint32_t gpu_prod_id = pan_prod_id(gpu_id);
for (unsigned i = 0; i < ARRAY_SIZE(pan_model_list); ++i) {
if (pan_model_list[i].gpu_prod_id == gpu_prod_id &&
pan_model_list[i].gpu_variant == gpu_variant)

31
src/panfrost/model/pan_model.h
View file

@ -22,8 +22,6 @@ struct pan_tiler_features {
unsigned max_levels;
};
#define MIDGARD_PRODUCT_ID(x) (((x) & BITFIELD_RANGE(16, 16)) >> 16)
#define PAN_ARCH_MAJOR(x) (((x) & BITFIELD_RANGE(28, 4)) >> 28)
#define PAN_ARCH_MINOR(x) (((x) & BITFIELD_RANGE(24, 4)) >> 24)
#define PAN_ARCH_REV(x) (((x) & BITFIELD_RANGE(20, 4)) >> 20)
@ -33,6 +31,17 @@ struct pan_tiler_features {
#define PAN_VERSION_MINOR(x) (((x) & BITFIELD_RANGE(4, 8)) >> 4)
#define PAN_VERSION_STATUS(x) ((x) & BITFIELD_RANGE(0, 4))
/* GPU product id for Midgard */
#define MIDGARD_PROD_ID(x) (((x) & BITFIELD_RANGE(16, 16)) >> 16)
/* GPU product id since Bifrost. Assume 8 bits per field which ensures the
* prod_id is always greater than Midgard's. */
#define PAN_PROD_ID(arch_major, arch_minor, prod_major) \
(((arch_major) << 16) | ((arch_minor) << 8) | (prod_major))
/* GPU revision (rXpY) */
#define PAN_REV(ver_major, ver_minor) (((ver_major) << 8) | ((ver_minor)))
struct pan_model {
/* GPU product ID */
uint32_t gpu_prod_id;
@ -88,7 +97,7 @@ const struct pan_model *pan_get_model(uint64_t gpu_id, uint32_t gpu_variant);
static inline unsigned
pan_arch(uint64_t gpu_id)
{
switch (MIDGARD_PRODUCT_ID(gpu_id)) {
switch (MIDGARD_PROD_ID(gpu_id)) {
case 0x600:
case 0x620:
case 0x720:
@ -104,4 +113,20 @@ pan_arch(uint64_t gpu_id)
}
}
static inline uint32_t
pan_prod_id(uint64_t gpu_id)
{
unsigned arch = pan_arch(gpu_id);
if (arch < 6)
return MIDGARD_PROD_ID(gpu_id);
return PAN_PROD_ID(PAN_ARCH_MAJOR(gpu_id), PAN_ARCH_MINOR(gpu_id),
PAN_PRODUCT_MAJOR(gpu_id));
}
static inline uint32_t
pan_rev(uint64_t gpu_id)
{
return PAN_REV(PAN_VERSION_MAJOR(gpu_id), PAN_VERSION_MINOR(gpu_id));
}
#endif