Commit graph

43489 commits

Author SHA1 Message Date
Eric Anholt
0bbbeba2db intel: Add support for blit copies of >32bpp formats.
The blitter only does up 32bpp at a time, so we handle it by mangling
coordinates and calling the surface 32bpp.

Fixes ARB_texture_rg/fbo-generatemipmap-formats-float with ARB_texture_float.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-20 10:35:42 -07:00
Eric Anholt
b31a99367c mesa: Add renderbuffer accessors for A, I, L, FLOAT32.
Of these, intel will be using I and L initially, and A once we rewrite
fragment shaders and the CC for rendering to it as R.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-20 10:35:42 -07:00
Eric Anholt
bad08969b5 mesa: Add renderbuffer accessors for MESA_FORMAT_R_FLOAT32, RG_FLOAT32.
Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-20 10:35:42 -07:00
Eric Anholt
f7c26109c2 mesa: Add ChooseTexFormat fallbacks for floating point textures.
This covers X_FLOAT16 -> X_FLOAT32, and X -> RGBA_FLOAT32.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-20 10:35:41 -07:00
Eric Anholt
ba99c2fbd9 mesa: Add renderbuffer accessors for MESA_FORMAT_RGBA_FLOAT32.
Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-20 10:35:41 -07:00
Eric Anholt
a45b757f78 swrast: Add LUMINANCE, INTENSITY, LUMINANCE_ALPHA to span asserts.
Fixes ARB_texture_float/fbo-alphatest-formats.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-20 10:35:41 -07:00
Alex Deucher
abee17057f r600g: fix userspace fences again
reinstate b7617346dc after the
rework in 6067a2a67f.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-04-20 13:09:09 -04:00
Fredrik Höglund
6067a2a67f r600g: don't flush the dest caches on every draw
Keep track of when the caches are dirty, and only flush them when
the framebuffer state is set and when the context is flushed.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-20 09:08:15 +10:00
Brian Paul
8b7f760f83 translate: disable clamping of instanced array indexes
This fixes piglit's draw-instanced-divisor test for softpipe on both
the generic and SSE paths.  This is temporary until we have the
correct per-array max_index information.
2011-04-19 16:13:47 -06:00
Alex Deucher
08d1c91e6c r600g: add evergreen+ big endian support
Based on Cédric's r6xx/r7xx patch.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-04-19 13:35:19 -04:00
Cédric Cano
843dfe3206 r600g: add big endian support for r6xx/r7xx
Signed-off-by: Cedric Cano <ccano@interfaceconcept.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-04-19 13:02:14 -04:00
Alex Deucher
b545b2987a r600c: add evergreen big endian support
Based on Cedric's r6xx/r7xx patch.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-04-19 12:06:52 -04:00
Cédric Cano
3c3a259603 r600c: add big endian support for r6xx/r7xx
Signed-off-by: Cedric Cano <ccano@interfaceconcept.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
2011-04-19 12:06:52 -04:00
Brian Paul
7a6061d7a6 Makefile: add missing Scons files 2011-04-19 09:07:44 -06:00
Thierry Vignaud
494b333b03 Makefile: add missing .cpp, .ll, .yy files
Signed-off-by: Brian Paul <brianp@vmware.com>
2011-04-19 08:34:06 -06:00
Dave Airlie
66866d642f r600g: add cb support for snorm formats.
Check for signed type and enable SNORM.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 20:44:13 +10:00
Marek Olšák
5722286be2 configure.ac: rename --enable-gallium-radeon to --enable-gallium-r300
Also fix up the help string for both r300 and r600.
2011-04-19 12:28:51 +02:00
Marek Olšák
ab13ebf7c1 r200: enable some extensions
Such as:
- GL_ARB_half_float_pixel
- GL_ARB_vertex_array_object
- GL_APPLE_vertex_array_object
- GL_EXT_gpu_program_parameters
2011-04-19 12:23:41 +02:00
Dave Airlie
c98fa6be4b r600g: fix warnings with piglit texture-rg test.
Fill in the swaps for the formats to fix warnings.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 18:45:58 +10:00
Dave Airlie
723e35d4a6 r600g: make loop const always flush
this needs revisiting, we really don't want to be flushing all 32 of these,
but currently we don't flush any of them, and it seems to have caused a regression
as reported on irc with doom3 on evergreen.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 16:39:50 +10:00
Tom Stellard
ffc1d166d2 r300/compiler: Fix dataflow analysis bug with ELSE blocks
Writes within ELSE blocks were being ignored which prevented us from
discovering all possible writers for some register values.

Fixes piglit glsl-fs-raytrace-bug27060
2011-04-18 21:27:03 -07:00
Bryan Cain
f41e1db327 glsl: fix conversions from uint to bool and from float/bool to uint
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
2011-04-18 17:09:47 -07:00
Dave Airlie
f05adb83f5 r600g: add dirty tracking to context reg.
just makes the code more consistent.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 10:12:20 +10:00
Dave Airlie
5b5a16e320 r600g: deinline some large functions.
really at these sort of sizes these are pointless inlines.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 10:12:20 +10:00
Dave Airlie
a6e32da8bd r600g: consolidate r600/evergreen code for resource emission.
These really didn't have much difference, and totally not inline material.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 10:12:20 +10:00
Bas Nieuwenhuizen
02522b76a1 r600g: don't flush caches if we already did so, even for a subset of the flags
Merging the flushes that are left doesn't seem to give a significant
performance improvement

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 10:12:20 +10:00
Dave Airlie
e3b9cf15bb r600g: attempt to avoid emitting resources that are the same
This just avoids reemitting resources that haven't changed.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 10:12:20 +10:00
Dave Airlie
162bc40eed r600g: modify block to only emit the first few dirty registers. (v2)
This gets me from 2200 to 1978 dwords for a gears frame.

This is due to us having some 32-dwords blocks in the SPI, that we only
modify the first dwords off.

v2: fix dirty reg count from Bas Nieuwenhuizen

Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 10:12:19 +10:00
Dave Airlie
c058067e57 r600g: track dirty registers better. (v2)
This is a first step to decreasing the CPU usage, by decreasing how much
stuff we pass to the GPU and hence to the kernel CS checker.

This adds a check to see if the values we need to write are actually dirty,
and avoids writing if they are. However certain register need to always
be written so we add a new flag to say which ones should be always written
if used. (Note this could probably be done cleaner with a larger refactoring,
 since I think the CONST_BUFFER_SIZE_PS/VS and CONST_CACHE_PS/VS might
be better off as a special state).

It also moves the need_bo to be a flags on the register now.

With this, a frame of gears goes from emitting 3k dwords to emitting 2k dwords,
and I'm sure it could get a lot smaller.

v2: fix some evergreen dirty bits.

Original patch from: Bas Nieuwenhuizen, I NIHed nearly the same thing
before seeing his patch on the list, oops.

Reviewed-by: Bas Nieuwenhuizen
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-04-19 10:12:19 +10:00
Ian Romanick
edf2e4f79d glsl: 80-column wrapping and whitespace fixes 2011-04-18 17:06:08 -07:00
Kenneth Graunke
ff5dd55e26 i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.
Most of the newer portions of the code use OUT_BATCH style.  I prefer
this style because it offers a clear distinction between a) hardware
messages/structures with a mandatory format, and b) data structures for
our own internal use that we can format however we want.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-18 15:26:34 -07:00
Kenneth Graunke
42a8057000 i965: Allocate the whole URB to the VS and fix calculations for Gen6.
Since we never enable the GS on Sandybridge, there's no need to allocate
it any URB space.

Furthermore, the previous calculation was incorrect: it neglected to
multiply by nr_vs_entries, instead comparing whether twice the size of
a single VS URB entry was bigger than the entire URB space.  It also
neglected to take into account that vs_size is in units of 128 byte
blocks, while urb_size is in bytes.

Despite the above problems, the calculations resulted in an acceptable
programming of the URB in most cases, at least on GT2.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2011-04-18 15:26:34 -07:00
Ian Romanick
3d5cfcfed1 glsl: Emit a warning when the left-hand operand of a comma has no effect
The expression

    x = y, 5, 3;

will generate

    0:7(9): warning: left-hand operand of comma expression has no effect

The warning is only emitted for the left-hand operands, becuase the
right-most operand is the result of the expression.  This could be
used in an assignment, etc.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2011-04-18 14:43:48 -07:00
Brian Paul
7ca38f5d97 mesa: fix void pointer arithmetic warnings
And fix a couple logic errors in the put_*_generic() functions.
2011-04-18 13:01:05 -06:00
Brian Paul
9418d05914 mesa: fix wrong parameter type in set_sampler_max_lod() 2011-04-18 12:43:42 -06:00
Brian Paul
1249e54f8b nvfx: comment-out unused var 2011-04-18 12:34:29 -06:00
Eric Anholt
dad95c112f intel: Add I8 and L8 to intel_mesa_format_to_rb_datatype().
Fixes warnings in fbo-storage-formats.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:54 -07:00
Eric Anholt
bc57df0356 Revert "intel: Add spans code for the ARB_texture_rg support."
This reverts what remains of commit
28bab24e16.  It was garbage, trying to
use a MESA_FORMAT enum as a preprocessor token, and I don't know how I
thought it was even tested.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:54 -07:00
Eric Anholt
73f0700481 intel: Use mesa core's R8, RG88, R16, RG1616 RB accessors.
Fixes:
ARB_texture_rg/fbo-alphatest-formats

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:54 -07:00
Eric Anholt
2b624634dd swrast: Don't try to adjust_colors for <8bpc when handling R16, RG1616.
The GL_RED and GL_RG were tricking this code into executing, but it's
totally unprepared for a 16-bit channel and just rescaled the values
down to 0.  We don't have anything with <8bit channels alongside >8bit
channels, so disabling it should be safe.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:54 -07:00
Eric Anholt
f0471d904c mesa: Add renderbuffer accessors for R8/RG88/R16/RG1616.
This will replace the current (broken by trying to use an enum in the
preprocessor) spantmp2.h support I wrote for the intel driver.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:54 -07:00
Eric Anholt
a52803e108 mesa: Use _mesa_get_format_bytes to refactor out the RB get_row_*
Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:54 -07:00
Eric Anholt
6ab9889a27 mesa: Use _mesa_get_format_bytes to refactor out the RB get_pointer_*
Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:54 -07:00
Eric Anholt
0778fdb002 intel: Use Mesa core's renderbuffer accessors for depth.
Since we're using GTT mappings now (no manual detiling), there's
really nothing special to accessing these buffers, other than needing
the new RowStride field of gl_renderbuffer to accomodate padding.

Reduces the driver size by 2.7kb, and improves glean depthStencil
performance 3-10x (!)

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:54 -07:00
Eric Anholt
9f164823c7 mesa: Add a function to set up the default renderbuffer accessors.
Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:53 -07:00
Eric Anholt
155200c154 mesa: Add a gl_renderbuffer.RowStride field like textures have.
This will allow some drivers to reuse the core renderbuffer.c get/put
row functions in place of using the spantmp.h macros.  Note that
unlike textures, we use a signed integer here to allow for handling
FBO orientation.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:53 -07:00
Eric Anholt
348ea34d03 mesa: Repack single-byte fields in gl_renderbuffer.
Cuts 8 out of 120 bytes in the struct.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:53 -07:00
Eric Anholt
91226ce648 mesa: Remove renderbuffer deletion debug field.
It has presumably served its purpose by now, and other object deletion
doesn't do this.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:53 -07:00
Eric Anholt
641dd899bd swrast: Don't assert against glReadPixels of GL_RED and GL_RG.
Everything appears to already be in place for this.  Fixes aborts in:
ARB_texture_rg/fbo-alphatest-formats-float
ARB_texture_rg/fbo-blending-formats-float.

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:53 -07:00
Eric Anholt
cd3568c329 intel: Use _mesa_base_tex_format for FBO texture attachments.
The _mesa_base_fbo_format variant doesn't handle some texture
internalformats, such as "3".

Fixes:
fbo-blending-formats.
fbo-alphatest-formats
EXT_texture_sRGB/fbo-alphatest-formats

Reviewed-by: Brian Paul <brianp@vmware.com>
2011-04-18 11:19:53 -07:00