Commit graph

201327 commits

Author SHA1 Message Date
Valentine Burley
ee72c8a177 ci/deqp: Remove non-suite support
Remove deqp-runner non-suite support to simplify deqp-runner.sh,
prevent the reintroduction of non-suite jobs, and streamline
testing.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32659>
2024-12-17 12:10:04 +00:00
Samuel Pitoiset
0223f0f54d radv: fix missing variants for the last VGT stage with shader object
Last VGT stages (VS, TES or GS) can always be used with a null FS when
nextStage is non-zero. Like if a VS is created with nextStage=TCS, it's
also allowed to draw without binding a CTS (ie. nextStage=None is always
a valid case).

Because we don't want to compile two variants for NONE and FRAGMENT,
let's compile only the FRAGMENT one when necessary.

Fixes new CTS coverage, see https://gerrit.khronos.org/c/vk-gl-cts/+/15976.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32665>
2024-12-17 09:50:52 +00:00
Samuel Pitoiset
5ad025b675 radv/ci: fix expected list of failures for TAHITI
DGC tests are skipped.

Fixes: dda03a21d6 ("Revert "radv: fix creating unlinked shaders with ESO when nextStage is 0"")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32672>
2024-12-17 09:49:14 +01:00
Valentine Burley
78f60e773c turnip/ci: Enable ASan leak detection in a630-vk-asan
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32652>
2024-12-17 07:44:03 +00:00
Valentine Burley
0615b92c23 radv/ci: Use deqp-vk-main in Raven and Stoney RADV jobs
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32647>
2024-12-17 07:23:03 +00:00
Kevin Chuang
1b55f10105 anv/bvh: Dump BVH synchronously upon command buffer completion
Modified the BVH dumping mechanism to synchronously wait for the command
buffer to complete before saving BVH data to files. This approach is
more robust compared to the previous method of dumping during
acceleration strucutre destruction.

Note: if DEBUG_BVH_ANY is enabled but intel-rt is disabled, we will wait
for nothing.

Signed-off-by: Kevin Chuang <kaiwenjon23@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32585>
2024-12-16 23:01:11 +00:00
Georg Lehmann
c695043e81 nir/opt_algebraic: optimize min(max(a, b), a)
Foz-DB Navi21:
Totals from 105 (0.13% of 79395) affected shaders:
MaxWaves: 2638 -> 2646 (+0.30%)
Instrs: 76531 -> 75077 (-1.90%)
CodeSize: 413668 -> 406484 (-1.74%)
VGPRs: 4856 -> 4848 (-0.16%)
Latency: 333684 -> 328438 (-1.57%); split: -1.57%, +0.00%
InvThroughput: 80417 -> 78579 (-2.29%)
VClause: 1818 -> 1768 (-2.75%)
SClause: 3028 -> 2964 (-2.11%)
Copies: 4708 -> 4513 (-4.14%); split: -4.50%, +0.36%
PreVGPRs: 3792 -> 3715 (-2.03%); split: -2.08%, +0.05%
VALU: 54734 -> 53528 (-2.20%)
SALU: 6195 -> 6137 (-0.94%)
VMEM: 2363 -> 2313 (-2.12%)
SMEM: 5219 -> 5119 (-1.92%)

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32634>
2024-12-16 22:29:21 +00:00
Marek Olšák
cdecbee922 radeonsi/gfx12: adjust HiZ/HiS logic
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32653>
2024-12-16 21:54:28 +00:00
Marek Olšák
e3cef02c24 radeonsi/gfx12: set DB_RENDER_OVERRIDE based on stencil state
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32653>
2024-12-16 21:54:28 +00:00
Marek Olšák
8328e57512 ac/surface/gfx12: enable DCC 256B compressed blocks and reorder modifiers
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32653>
2024-12-16 21:54:27 +00:00
Marek Olšák
e6345e2fd3 ac: update SPI_GRP_LAUNCH_GUARANTEE_* register values for gfx12
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32653>
2024-12-16 21:54:27 +00:00
Georg Lehmann
0e6d32777f nir/opt_remove_phis: rematerialize equal alu
Foz-DB Navi31:
Totals from 943 (1.19% of 79395) affected shaders:
MaxWaves: 24672 -> 24722 (+0.20%)
Instrs: 1541665 -> 1544956 (+0.21%); split: -0.23%, +0.44%
CodeSize: 8085180 -> 8109212 (+0.30%); split: -0.16%, +0.46%
VGPRs: 57768 -> 57624 (-0.25%)
Latency: 18043743 -> 17948245 (-0.53%); split: -1.28%, +0.75%
InvThroughput: 2692605 -> 2677049 (-0.58%); split: -2.07%, +1.49%
VClause: 25321 -> 25343 (+0.09%); split: -0.48%, +0.57%
SClause: 38473 -> 38614 (+0.37%); split: -0.00%, +0.37%
Copies: 86089 -> 86236 (+0.17%); split: -0.46%, +0.63%
Branches: 36719 -> 36777 (+0.16%); split: -0.60%, +0.76%
PreSGPRs: 44138 -> 44303 (+0.37%); split: -0.05%, +0.42%
PreVGPRs: 43319 -> 43009 (-0.72%)
VALU: 893684 -> 894272 (+0.07%); split: -0.42%, +0.48%
SALU: 189561 -> 191358 (+0.95%); split: -0.05%, +1.00%
VMEM: 42294 -> 42313 (+0.04%); split: -0.44%, +0.49%
SMEM: 72916 -> 73144 (+0.31%)

Instruction count regressions are largly caused by additional
loop unrolling.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31028>
2024-12-16 20:38:38 +00:00
Aleksi Sapon
c0a0953476 llvmpipe: PointCoord is offset when multisampling is enabled
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32578>
2024-12-16 20:15:59 +00:00
Samuel Pitoiset
dda03a21d6 Revert "radv: fix creating unlinked shaders with ESO when nextStage is 0"
This reverts commit d4ccae739b.

This is actually unnecessary. nextStage=0 means it's the last stage.
Looks like the specification was too vague and we misinterpreted it.

It's going to be clarified and VKCTS will be fixed, see
https://gitlab.khronos.org/vulkan/vulkan/-/issues/4115 for more info.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32629>
2024-12-16 19:31:57 +01:00
Samuel Pitoiset
0943f616d1 radv: report same buffer aligment for DGC preprocessed buffer
It makes sense to report the same alignment.

This fixes new VKCTS coverage.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32626>
2024-12-16 14:53:56 +00:00
Erik Faye-Lund
336e2c90ce docs: add new panvk features
We're not really in the habit of updating new_features.txt for panvk,
but let's get this up to date.

Acked-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32586>
2024-12-16 15:32:20 +01:00
Erik Faye-Lund
9a8e291d45 panvk: make vk-version helper internal to source
This is no longer needed outside of this single source file, so let's
no longer make it available outside.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32654>
2024-12-16 12:10:50 +00:00
Erik Faye-Lund
42bfbe1a94 panvk: back out of vk 1.1 support
Supporting Vulkan 1.1 was premature, as we don't support subgroup
operations, which are actually required (even if it's not listed in
section "46.1. Feature Requirements"):

Here's the relevant phrasing from the Vulkan 1.1 spec:

> subgroupSupportedOperations will have the VK_SUBGROUP_FEATURE_BASIC_BIT
> bit set if any of the physical device’s queues support
> VK_QUEUE_GRAPHICS_BIT or VK_QUEUE_COMPUTE_BIT.

So, it seems we have to support at least the basic feature set before we
can expose Vulkan 1.1. So let's back out of that for now.

Fixes: a6e03ce428 ("panvk: advertise version 1.1 support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32654>
2024-12-16 12:10:50 +00:00
Valentine Burley
da18cd9f9a softpipe/ci: Convert softpipe-asan-gles31 to a deqp-runner suite
Due to the differences in how the caselists are generated, there is
a discrepancy in the failures encountered. Update the expectations
accordingly.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32622>
2024-12-16 11:27:31 +00:00
Valentine Burley
309dc3c43f etnaviv/ci: Convert to deqp-runner suites
Convert gc2000-gles2 and gc7000-gles2 to deqp-runner suites.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32622>
2024-12-16 11:27:31 +00:00
Valentine Burley
b30323d77d lavapipe/ci: Convert lavapipe-vk-asan to a deqp-runner suite
This is a currently disabled job. Convert it to a deqp-runner
suite, but don't enable it yet as it is still broken.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32622>
2024-12-16 11:27:31 +00:00
Juan A. Suarez Romero
fd19106773 broadcom/compiler: fix fp16 conversion operations
The case for converting a 32-bit integer to 16-bit float is not
correctly implemented.

Fixes: 214121e9b0 ("broadcom/compiler: handle fp16 conversion ops")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32593>
2024-12-16 10:56:38 +00:00
Juan A. Suarez Romero
8ffdf5a2ab broadcom/compiler: ensure offset source exists
As the lowering is applied on a load uniform intrinsic, there must be an
offset source number.

This fixes CID#1604734 ("Negative array index read") detected by
Coverity Scan.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32593>
2024-12-16 10:56:38 +00:00
Juan A. Suarez Romero
15dfcd0db3 v3dv: ensure there is always a perfmon and counter
Helps static analyzer to don't complain about (potential) reading
unitialized values.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32593>
2024-12-16 10:56:38 +00:00
Juan A. Suarez Romero
13581b7380 v3dv: free pointers on multisync error
Free pointers if set_multisync() fails.

This fixes several leaks detected by static analyzer.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32593>
2024-12-16 10:56:38 +00:00
Juan A. Suarez Romero
f6766ccadb v3dv: fix BO allocation
`cleared_and_retried` variable is not required, as once the cache is
empty, in the second retry it will retry it is already empty so it won't
retry a new allocation.

Fixes: 2adea940f1 ("v3dv/bo: adding a BO cache")
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32593>
2024-12-16 10:56:38 +00:00
Juan A. Suarez Romero
cb9650d1a2 v3dv: remove unused assignments
These variables are not used later in the code.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32593>
2024-12-16 10:56:38 +00:00
Erik Faye-Lund
c5c11481dd panvk: only validate the push-sets that we update
We are conditionally updating the push-sets, so we need to also
conditionally clear the dirty-flags here instead of clearing them
wholesale. Otherwise, we end up not updating the descriptors that are
used in subsequent draws, but not in the first one.

Fixes: 79e5146378 ("panvk: Sanitize the driver-internal dirty state tracking")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32630>
2024-12-16 10:16:05 +01:00
Erik Faye-Lund
9531f6375f panvk: fixup bad indent
We use spaces, not tabs.

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32630>
2024-12-16 10:16:05 +01:00
You, Min-Hsuan
22ff26a0be amd/vpelib: fix coverity defects
\[WHY\]
The reason for making these changes is to address the defects identified
by the Coverity scan. By fixing these defects, we can ensure that any
future defects generated by our own code changes can be easily
identified and resolved.

\[HOW\]
To implement the changes/fixes, the following steps were taken:

1. CHECKED_RETURN: All cases were aligned to check the return value.
2. DC.WEAK_CRYPTO: The use of rand() to generate random numbers was
replaced with a more secure method using platofrm API.
3. DEADCODE: Useless code that always returned true was removed.
4. DIVIDE_BY_ZERO: A check was added to ensure that the divisor is not
zero before performing division.
5. HFA: An unused header was removed.
6. MISSING_BREAK: A break statement was added in switch cases where it
was missing.
7. PASS_BY_VALUE: Parameters that were being passed by value and were
too big were changed to pass by reference.

\[TESTING\]
What testings have been done (test IDs and json file):

Reviewed-by: Tomson Chang <Tomson.Chang@amd.com>
Signed-off-by: Min-Hsuan You <Min-Hsuan.You@amd.com>
Acked-by: Chenyu Chen <Chen-Yu.Chen@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32646>
2024-12-16 08:13:40 +00:00
Koo, Anthony
54c4accdb1 amd/vpelib: Add system event logging
\[WHY\]
System event logs are different than string logging. They are meant to
generate light weight events with ID and variable args and can be
coalesced with events generated by other IP components.

\[HOW\]
Add a callback function, which is implemented by the client (Like PAL)

VPELIB adds defines for a list of possible event IDs

The client is expected to handle the callback
And translate and emit the event through
native system infrastructure like ETW logging.

\[TESTING\]
Tested on system that triggers sys event, and viewed the event through
ETW viewer

Signed-off-by : Anthony Koo <anthony.koo@amd.com>

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chenyu Chen <Chen-Yu.Chen@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32646>
2024-12-16 08:13:40 +00:00
Zhao, Jiali
fe58bb70e6 amd/vpelib: 420 and 422 Output Single Segment cositing support
fix the style complaint
add 709 jfif color space handling

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Signed-off-by: Jiali Zhao <Jiali.Zhao@amd.com>
Acked-by: Chenyu Chen <Chen-Yu.Chen@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32646>
2024-12-16 08:13:40 +00:00
Visan, Tiberiu
b06ee9074d amd/vpelib: fixed file headers for Palamida scan
\[WHY\]
Some header files in VPE lib did not have the proper copyright header

\[HOW\]
Proper copyrights were put in place

Reviewed-by: Roy Chan <roy.chan@amd.com>
Co-authored-by: Tiberiu Visan <tvisan@amd.com>
Acked-by: Chenyu Chen <Chen-Yu.Chen@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32646>
2024-12-16 08:13:40 +00:00
Leder, Brendan Steve
4ef45d8d4e amd/vpelib: Move bg color
Refactor bg gen as it check_bg_support simply calls into other version specific function.
Move that function directly into check_bg_support call, and refactor unnecessary functions + format fix.

Co-authored-by: Brendan <breleder@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com>
Acked-by: Chenyu Chen <Chen-Yu.Chen@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32646>
2024-12-16 08:13:40 +00:00
Marek Olšák
3943ed8199 ac/lower_ngg: improve streamout code generation for gfx12/ACO to match LLVM
ACO is still not perfect:
* It generates s_wait_loadcnt 0x0-0x3 when the only required wait instruction
  is s_wait_loadcnt 0x5.
* It generates a lot of unnecessary jumps and blocks for uniform loop breaks.
  Only scc1 jumps are necessary to break the loop. This is 10x better than
  LLVM, but even ACO might consider using nir_intrinsic_ordered_add_loop_gfx12_amd
  for the best performance.

How to print the streamout asm on any GPU:
    PIGLIT_PLATFORM=gbm AMD_FORCE_FAMILY=gfx12_16pipe AMD_DEBUG=vs,mono,asm,useaco ../piglit/bin/shader-io-rate vs_out_xfb

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:07 +00:00
Qiang Yu
d38efee8ef aco: enable gfx12 support for radeonsi
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:07 +00:00
Qiang Yu
129e37bab6 nir: do not generate b2i64 when driver want to lower it
This is found on GFX12 by:
  KHR-GL43.shader_ballot_tests.ShaderBallotBitmasks

ACO does not support it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:07 +00:00
Qiang Yu
12ea316a05 radeonsi: add AMD_FORCE_SHADER_USE_ACO for debug
Narrow down ACO compiler problem to a single shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Qiang Yu
679c450184 util/blake3: add _mesa_blake3_from_printed_string
To convert printed blake3 string back to blake3 hash.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Qiang Yu
0fd99353a6 radeonsi: disable use_gfx12_xfb_intrinsic when use ACO
ACO does not implement nir_ordered_add_loop_gfx12_amd which is for
LLVM only.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Qiang Yu
b14cc34415 ac/surf: add more modifiers to gfx12 supported list
OpenGL will export these modifiers for various sized
textures.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Qiang Yu
b3a218d444 ac/surface/tests: support all block sizes
We are going to add more modifiers.

GFX9 has 4K DCC and non-DCC modifiers while others only have
4K non-DCC modifiers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32570>
2024-12-16 07:35:06 +00:00
Caio Oliveira
93dfe504f2 intel/brw: Add SHADER_OPCODE_READ_FROM_CHANNEL and LIVE_CHANNEL
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32412>
2024-12-14 11:38:14 -08:00
Job Noorman
4d04396531 ir3/validate: print file/line info
This makes it much easier to spot where a validation error comes from as
many assert are similar so difficult to grep for.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32623>
2024-12-14 06:05:26 +00:00
Caio Oliveira
d325de316d intel/brw: Add some tests for new Xe2 register regioning restrictions
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
2024-12-14 02:15:18 +00:00
Caio Oliveira
f308be16a0 intel/brw: Add validation for some Xe2 register regioning restrictions
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
2024-12-14 02:15:18 +00:00
Caio Oliveira
6a5a316312 intel/brw: Extract format enum in EU validation code
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
2024-12-14 02:15:18 +00:00
Caio Oliveira
57b703cec3 intel/brw: Skip some regioning EU validation for Vx1 and VxH modes
Skip the ones that check the VertStride -- which is set to a special
value in those modes.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
2024-12-14 02:15:18 +00:00
Kenneth Graunke
d85d6ad2a5 iris: Tune the BO cache's bucket sizes
With the introduction of the slab allocator, most of our small
allocations now hit that rather than directly hitting the bucket
cache.  Those now show up as 2MB slab allocations from the cache's
perspective.  So, we don't need quite as many buckets.  (Note that
only allocations in IRIS_MEMZONE_OTHER are suballocated today.)

Previously, we had 55 buckets, going from 4KB to 112MB, with sizes
N, N+1/4, N+1/2, N+3/4 for a series of power-of-two N's.

This patch prunes it down to 25 buckets:

   - 4K-4MB => power-of-two sizes only
   - 6MB    => a one-off bucket to reduce waste between 4MB and 8MB
   - 8MB+   => the usual N, N+1/4, N+1/2, N+3/4 system
   - 64MB   => the largest bucket size

In particular, this eliminates the 1.75MB, 2.5MB, 3MB, 3.5MB, and 7MB
buckets in favor of multiples of 2MB.  Allocating multiples of 2MB is
preferable because it allows the kernel to allocate 64KB pages rather
than being stuck using inefficient 4K pages.  And, the amount of waste
from bumping to the next multiple of 2MB isn't huge in that range of
sizes.  We also eliminate buckets larger than 64MB because they're
rarely used, and also the amount of waste from rounding up to the
80/96/112MB buckets can get pretty large.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Fixes: 0b6693a3a1 ("iris: Align fresh BO allocations to 2MB in size")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10219
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32635>
2024-12-13 15:37:09 -08:00
Felix DeGrood
0f46c53b0c anv: Use vfg distribution mode = RR_STRICT for Xe2+
Performance tuning. Round Robin strict faster on Xe2 for some
workloads.

Speedup:
 - Borderlands3-dx11-trace: +4%
 - WolfensteinYoungblood-vk.g6: +1.5%
 - Cyberpunk2077-dx12vk-2160p-ultra: +0.5%

Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32566>
2024-12-13 19:15:48 +00:00