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intel/brw: Add validation for some Xe2 register regioning restrictions
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28636>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
6a5a316312
commit
f308be16a0
1 changed files with 153 additions and 0 deletions
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@ -2184,6 +2184,158 @@ send_descriptor_restrictions(const struct brw_isa_info *isa,
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return error_msg;
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}
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static struct string
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register_region_special_restrictions(const struct brw_isa_info *isa,
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const brw_hw_decoded_inst *inst)
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{
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const struct intel_device_info *devinfo = isa->devinfo;
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struct string error_msg = { .str = NULL, .len = 0 };
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bool format_uses_regions = inst->format == FORMAT_BASIC ||
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inst->format == FORMAT_BASIC_THREE_SRC;
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/* "Src0 Restrictions" in "Special Restrictions" in Bspec 56640 (r57070). */
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if (devinfo->ver >= 20 &&
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format_uses_regions &&
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inst->num_sources > 0 &&
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inst->src[0].file == FIXED_GRF) {
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const unsigned v = inst->src[0].vstride;
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const unsigned w = inst->src[0].width;
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const unsigned h = inst->src[0].hstride;
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const bool multi_indirect =
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inst->src[0].address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER &&
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inst->src[0].vstride == STRIDE(BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL);
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const bool is_Vx1 = multi_indirect && w != 1;
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const bool is_VxH = multi_indirect && w == 1;
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const unsigned src0_stride = w == 1 ? v : h;
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const unsigned src0_uniform_stride = (w == 1) || (h * w == v) || is_Vx1;
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const unsigned dst_stride = inst->dst.hstride;
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const unsigned src0_size = brw_type_size_bytes(inst->src[0].type);
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const unsigned dst_size = brw_type_size_bytes(inst->dst.type);
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const unsigned src0_subnr = inst->src[0].subnr / src0_size;
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const unsigned dst_subnr = inst->dst.subnr / dst_size;
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const bool dst_dword_aligned = (dst_size >= 4) ||
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(dst_size == 2 && (dst_subnr % 2 == 0)) ||
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(dst_size == 1 && (dst_subnr % 4 == 0));
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/* The section below follows the pseudo-code in the spec to make
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* easier to verify.
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*/
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bool allowed = false;
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if ((dst_size >= 4) ||
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(src0_size >= 4) ||
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(dst_size == 2 && dst_stride > 1) ||
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(dst_size == 1 && dst_stride > 2) ||
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is_VxH) {
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/* One element per DWord channel. */
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allowed = true;
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} else if (src0_uniform_stride || dst_dword_aligned) {
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if (src0_size == 2 && dst_size == 2) {
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if ((src0_stride < 2) ||
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(src0_stride == 2 && src0_uniform_stride && (dst_subnr % 16 == src0_subnr / 2)))
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allowed = true;
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} else if (src0_size == 2 && dst_size == 1 && dst_stride == 2) {
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if ((src0_stride < 2) ||
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(src0_stride == 2 && src0_uniform_stride && (dst_subnr % 32 == src0_subnr)))
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allowed = true;
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} else if (src0_size == 1 && dst_size == 2) {
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if ((src0_stride < 4) ||
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(src0_stride == 4 && src0_uniform_stride && ((2 * dst_subnr) % 16 == src0_subnr / 2)) ||
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(src0_stride == 8 && src0_uniform_stride && ((2 * dst_subnr) % 8 == src0_subnr / 4)))
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allowed = true;
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} else if (src0_size == 1 && dst_size == 1 && dst_stride == 2) {
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if ((src0_stride < 4) ||
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(src0_stride == 4 && src0_uniform_stride && (dst_subnr % 32 == src0_subnr / 2)) ||
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(src0_stride == 8 && src0_uniform_stride && (dst_subnr % 16 == src0_subnr / 4)))
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allowed = true;
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} else if (src0_size == 1 && dst_size == 1 && dst_stride == 1 && w != 2) {
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if ((src0_stride < 2) ||
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(src0_stride == 2 && src0_uniform_stride && (dst_subnr % 32 == src0_subnr / 2)) ||
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(src0_stride == 4 && src0_uniform_stride && (dst_subnr % 16 == src0_subnr / 4)))
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allowed = true;
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} else if (src0_size == 1 && dst_size == 1 && dst_stride == 1 && w == 2) {
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if ((h == 0 && v < 4) ||
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(h == 1 && v < 4) ||
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(h == 2 && v < 2) ||
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(h == 1 && v == 4 && (dst_subnr % 32 == 2 * (src0_subnr / 4)) && (src0_subnr % 2 == 0)) ||
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(h == 2 && v == 4 && (dst_subnr % 32 == src0_subnr / 2)) ||
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(h == 4 && v == 8 && (dst_subnr % 32 == src0_subnr / 4)))
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allowed = true;
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}
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}
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ERROR_IF(!allowed,
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"Invalid register region for source 0. See special restrictions section.");
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}
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/* "Src1 Restrictions" in "Special Restrictions" in Bspec 56640 (r57070). */
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if (devinfo->ver >= 20 &&
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format_uses_regions &&
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inst->num_sources > 1 &&
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inst->src[1].file == FIXED_GRF) {
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const unsigned v = inst->src[1].vstride;
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const unsigned w = inst->src[1].width;
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const unsigned h = inst->src[1].hstride;
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const bool multi_indirect =
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inst->src[1].address_mode == BRW_ADDRESS_REGISTER_INDIRECT_REGISTER &&
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inst->src[1].vstride == STRIDE(BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL);
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const bool is_Vx1 = multi_indirect && w != 1;
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const unsigned src1_stride = w == 1 ? v : h;
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const unsigned src1_uniform_stride = (w == 1) || (h * w == v) || is_Vx1;
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const unsigned dst_stride = inst->dst.hstride;
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const unsigned src1_size = brw_type_size_bytes(inst->src[1].type);
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const unsigned dst_size = brw_type_size_bytes(inst->dst.type);
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const unsigned src1_subnr = inst->src[1].subnr / src1_size;
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const unsigned dst_subnr = inst->dst.subnr / dst_size;
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const bool dst_dword_aligned = (dst_size >= 4) ||
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(dst_size == 2 && (dst_subnr % 2 == 0)) ||
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(dst_size == 1 && (dst_subnr % 4 == 0));
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/* The section below follows the pseudo-code in the spec to make
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* easier to verify.
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*/
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bool allowed = false;
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if ((dst_size >= 4) ||
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(src1_size >= 4) ||
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(dst_size == 2 && dst_stride > 1) ||
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(dst_size == 1 && dst_stride > 2)) {
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/* One element per DWord channel. */
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allowed = true;
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} else if (src1_uniform_stride || dst_dword_aligned) {
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if (src1_size == 2 && dst_size == 2) {
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if ((src1_stride < 2) ||
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(src1_stride == 2 && src1_uniform_stride && (dst_subnr % 16 == src1_subnr / 2)))
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allowed = true;
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} else if (src1_size == 2 && dst_size == 1 && dst_stride == 2) {
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if ((src1_stride < 2) ||
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(src1_stride == 2 && src1_uniform_stride && (dst_subnr % 32 == src1_subnr)))
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allowed = true;
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}
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}
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ERROR_IF(!allowed,
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"Invalid register region for source 1. See special restrictions section.");
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}
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return error_msg;
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}
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static struct string
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scalar_register_restrictions(const struct brw_isa_info *isa,
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const brw_hw_decoded_inst *inst)
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@ -2652,6 +2804,7 @@ brw_validate_instruction(const struct brw_isa_info *isa,
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CHECK(special_requirements_for_handling_double_precision_data_types);
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CHECK(instruction_restrictions);
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CHECK(send_descriptor_restrictions);
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CHECK(register_region_special_restrictions);
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CHECK(scalar_register_restrictions);
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}
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