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radv: report same buffer aligment for DGC preprocessed buffer

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It makes sense to report the same alignment.

This fixes new VKCTS coverage.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32626>
This commit is contained in:
Samuel Pitoiset 2024-12-13 12:29:47 +01:00 • committed by Marge Bot
parent 336e2c90ce
commit 0943f616d1
3 changed files with 20 additions and 5 deletions
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11
src/amd/vulkan/radv_buffer.c
View file

@ -11,6 +11,7 @@
#include "radv_buffer.h"
#include "radv_device.h"
#include "radv_device_memory.h"
#include "radv_dgc.h"
#include "radv_entrypoints.h"
#include "radv_instance.h"
#include "radv_physical_device.h"
@ -201,10 +202,14 @@ radv_get_buffer_memory_requirements(struct radv_device *device, VkDeviceSize siz
VK_BUFFER_USAGE_2_SAMPLER_DESCRIPTOR_BUFFER_BIT_EXT | VK_BUFFER_USAGE_2_PREPROCESS_BUFFER_BIT_EXT))
pMemoryRequirements->memoryRequirements.memoryTypeBits = pdev->memory_types_32bit;
if (flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
if (flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
pMemoryRequirements->memoryRequirements.alignment = 4096;
else
pMemoryRequirements->memoryRequirements.alignment = 16;
} else {
if (usage & VK_BUFFER_USAGE_2_PREPROCESS_BUFFER_BIT_EXT)
pMemoryRequirements->memoryRequirements.alignment = radv_dgc_get_buffer_alignment(device);
else
pMemoryRequirements->memoryRequirements.alignment = 16;
}
/* Top level acceleration structures need the bottom 6 bits to store
* the root ids of instances. The hardware also needs bvh nodes to

11
src/amd/vulkan/radv_dgc.c
View file

@ -57,6 +57,14 @@
* trailer
*/
uint32_t
radv_dgc_get_buffer_alignment(const struct radv_device *device)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
return MAX2(pdev->info.ip[AMD_IP_GFX].ib_alignment, pdev->info.ip[AMD_IP_COMPUTE].ib_alignment);
}
static uint32_t
radv_pad_cmdbuf(const struct radv_device *device, uint32_t size, enum amd_ip_type ip_type)
{
@ -2742,8 +2750,7 @@ radv_GetGeneratedCommandsMemoryRequirementsEXT(VkDevice _device,
get_dgc_cmdbuf_layout(device, layout, pInfo->pNext, pInfo->maxSequenceCount, true, &cmdbuf_layout);
pMemoryRequirements->memoryRequirements.memoryTypeBits = pdev->memory_types_32bit;
pMemoryRequirements->memoryRequirements.alignment =
MAX2(pdev->info.ip[AMD_IP_GFX].ib_alignment, pdev->info.ip[AMD_IP_COMPUTE].ib_alignment);
pMemoryRequirements->memoryRequirements.alignment = radv_dgc_get_buffer_alignment(device);
pMemoryRequirements->memoryRequirements.size =
align(cmdbuf_layout.alloc_size, pMemoryRequirements->memoryRequirements.alignment);
}

3
src/amd/vulkan/radv_dgc.h
View file

@ -14,6 +14,7 @@
#include "vk_device_generated_commands.h"
struct radv_cmd_buffer;
struct radv_device;
enum radv_queue_family;
struct radv_indirect_command_layout {
@ -45,6 +46,8 @@ struct radv_indirect_execution_set {
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_indirect_execution_set, base, VkIndirectExecutionSetEXT,
VK_OBJECT_TYPE_INDIRECT_EXECUTION_SET_EXT);
uint32_t radv_dgc_get_buffer_alignment(const struct radv_device *device);
uint32_t radv_get_indirect_main_cmdbuf_offset(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);
uint32_t radv_get_indirect_ace_cmdbuf_offset(const VkGeneratedCommandsInfoEXT *pGeneratedCommandsInfo);