Commit graph

201327 commits

Author SHA1 Message Date
Nicolai Haehnle
1170268088 r300: Fix warnings that were introduced by the glsl merge 2007-03-26 21:41:57 +02:00
Brian
38a1c2b495 Add _swrast_span_default_secondary_color() for use with glBitmap, glDrawPixels, etc.
Secondary color wasn't getting added to post-texture color when drawing
bitmaps, images.  See bug 10409.
2007-03-26 11:30:05 -06:00
Brian
b5d988dd19 remove incorrect assertions 2007-03-26 10:39:56 -06:00
Brian
b67d93111d minor status updates 2007-03-26 10:23:50 -06:00
Brian
22d9132081 disable printing shader program debug info 2007-03-26 10:15:02 -06:00
Brian
d619cceea4 merge of glsl-compiler-1 branch 2007-03-26 10:13:02 -06:00
Michel Dänzer
76f3b66e04 i915tex: Make sure renderbuffers don't get deleted when flipping them.
Since the recent renderbuffer refcounting fixes it's no longer sufficient to
just remove the old renderbuffer from the framebuffer and then add the new one
because the former may decrease the reference count to 0 and delete the old
renderbuffer.
2007-03-26 17:38:58 +02:00
Brian
e71c34aaa1 disable free() until other issues can be fixed... 2007-03-26 09:24:30 -06:00
Brian
b9fbedd601 fix mem leak, add comments 2007-03-26 09:23:44 -06:00
Ben Skeggs
8051c95a7e nouveau: match drm version bump 2007-03-26 21:31:43 +10:00
Nian Wu
ee9bc897f8 Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline 2007-03-26 17:00:29 +08:00
Brian
42aaa548a1 Fix some renderbuffer reference counting issues. Also fixes a mem leak. 2007-03-25 10:39:36 -06:00
Brian
6fda763989 destroy window on exit 2007-03-25 10:25:29 -06:00
Xiang, Haihao
a1ea7812b2 i965: The given urb layout(maximal size of urb entries and the
values for nr of entries) should meet the requirement.
2007-03-25 21:40:58 +08:00
Xiang, Haihao
bb59d81d2d Color3iv: set the alpha value to 1.0 2007-03-25 21:31:36 +08:00
Nicolai Haehnle
8a4546b561 r300: Whitespace cleanup in r300_texmem.c 2007-03-25 14:57:56 +02:00
Nicolai Haehnle
9db583e7e4 r300: Whitespace cleanup in r300_texstate.c 2007-03-25 14:57:49 +02:00
Nicolai Haehnle
7143c61283 r300: Fix regression: unnecessary node indirection
The texture_rectangle fix introduced a bug where every texture instruction
caused a new indirection.
2007-03-25 13:04:03 +02:00
Nian Wu
1b354bb5e4 Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline 2007-03-25 17:00:24 +08:00
Brian
bb0393a0cd fix mem leak 2007-03-24 16:44:20 -06:00
Brian
9fe342d1e6 disable free(var->aux) -- can lead to segfault 2007-03-24 16:43:44 -06:00
Brian
cfdd07d7d3 fix mem leak 2007-03-24 16:26:51 -06:00
Brian
1968444bed fix some mem leaks 2007-03-24 16:22:35 -06:00
Brian
935f93f966 Free shader-related context state: _mesa_free_shader_state() 2007-03-24 16:20:02 -06:00
Brian
3493e867e9 free prog->Attributes in _mesa_delete_program() 2007-03-24 16:18:13 -06:00
Brian
49134e8e53 fix mistake in _slang_free_ir() 2007-03-24 15:29:10 -06:00
Dave Airlie
74ceaf545f nouveau: implement nv20Clear and nv20Scissor
Still crashes out on scissor regs
2007-03-25 07:09:02 +10:00
Nicolai Haehnle
f27991c916 r300: Fix texture coordinate calculation for rectangle textures
R300 hardware takes texcoords in the range 0..1 even for rectangle
textures. Previously, the necessary texcoord conversion was applied
to the texture coordinate during vertex processing in a render stage.

This is obviously wrong when fragment programs are used, which can
calculate arbitrary coordinates for TEX instructions. Therefore,
we now inject an appropriate MUL instruction before a TEX that
reference a rectangle texture.
2007-03-24 19:09:44 +01:00
Nicolai Haehnle
0c3ae2ea7f r300: No assertion when accessing incomplete texture images.
There used to be an assertion when a fragment program accesses an incomplete
texture image. Work around this assertion.
Note: I am unsure whether this workaround produces the desired result
(0,0,0,1) on all hardware.
2007-03-24 18:11:37 +01:00
Brian
0e71d08e8d Properly free the slang_ir_node->Store data (use ref counting). 2007-03-24 10:18:14 -06:00
Brian
b50b036ffb When computing render_inputs_bitset, omit primary color if we have a fragment program and it doesn't need FRAG_ATTRIB_COL0. Silences valgrind warnings. 2007-03-24 10:16:49 -06:00
Brian
dc3015f157 move some code into new slang_ir.c file 2007-03-24 09:40:20 -06:00
Brian
b2bc563142 IR utility functions 2007-03-24 09:39:24 -06:00
Nicolai Haehnle
d4dd5a95a8 r300: Fix: KIL instruction don't require textures
When no textures were enabled, a KIL instruction triggered an assertion
in r300_setup_rs_unit.
2007-03-24 14:43:06 +01:00
Nicolai Haehnle
8f90822b72 swrast: Fix crash when sampling from a non-existing texture object 2007-03-24 14:42:49 +01:00
Ben Skeggs
ea3d11a3d8 nouveau: some swtcl fixes 2007-03-24 22:24:00 +11:00
Nian Wu
44fb5156bb Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline 2007-03-24 17:00:29 +08:00
Brian
8e1c3bd0b4 Implement alpha buffer copy for SwapBuffers().
Nicolai writes:
When the pixmap pixel format has no alpha channel, the x11 driver
(software rendering) adds a wrapped alpha channel on request.

During SwapBuffers, this alpha channel is not copied from back to
front, which means that the front buffer doesn't really contain the
contents that the back buffer previously contained.

A subsequent glReadPixels from the front buffer will return an
incorrect result. The following patch attempts to fix this.
2007-03-23 18:01:31 -06:00
Brian
8f9db0f81c document internal compiler options 2007-03-23 17:49:19 -06:00
Brian
d1934c2065 Fix issues related to the 'continue' statement.
IR_LOOP now has two children: the body code, and the tail code.
Tail code is the "i++" part of a for-loop, or the expression at the end
of a "do {} while(expr);" loop.
"continue" translates into: "execute tail code; CONT;"
Also, the test for infinite do/while loops was incorrect.
2007-03-23 17:48:42 -06:00
Brian
81767eead9 consolidate some code 2007-03-23 17:45:53 -06:00
Brian
63556fa994 Add the ability to generate programs that doesn't use condition codes.
ctx->Shader.EmitCondCodes determines if we use condition codes.
If not, IF statement uses first operand's X component as the condition.
Added OPCODE_BRK0, OPCODE_BRK1, OPCODE_CONT0, OPCODE_CONT1 to handle
the common cases of conditional break/continue.
2007-03-23 14:47:46 -06:00
Brian
bf020d8d7f minor tweaks 2007-03-23 14:44:34 -06:00
Brian
2bdac09d16 updated comment 2007-03-23 10:46:08 -06:00
Nicolai Haehnle
654a308439 r300: Whitespace cleanup (remove trailing spaces) 2007-03-23 17:39:28 +01:00
Nian Wu
ad76128204 Merge git://proxy01.pd.intel.com:9419/git/mesa/mesa into crestline 2007-03-23 17:00:28 +08:00
Brian
fe20a619cf updated comment 2007-03-22 16:07:43 -06:00
Brian
e6aeb24b23 Overhaul emit_compare() function.
Previously, comparing vec2, vec3, vec4 was broken.
Added IR_EQUAL, IR_NOTEQUAL nodes/operators to compute boolean
equality/inequality vs. IR_SEQUAL/IR_SNEQUAL which work component-wise.
Use IR_EQUAL/IR_NOTEQUAL for the == and != operators.
To compute vec4 equality, use SNE, DP4, SEQ instruction sequence.
2007-03-22 16:07:14 -06:00
Brian
0aad9e2627 First pass at implementing structure compares.
Need to improve this.  There may be holes in a structure so we can't
just blindly compare the full 4-float registers.
2007-03-22 09:15:39 -06:00
Brian
12229f119d use _mesa_copy_instructions() 2007-03-22 09:11:26 -06:00