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https://gitlab.freedesktop.org/mesa/mesa.git
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r300: Whitespace cleanup in r300_texmem.c
This commit is contained in:
Nicolai Haehnle
parent
9db583e7e4
commit
8a4546b561
1 changed files with 163 additions and 168 deletions
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@ -303,195 +303,190 @@ static void r300UploadRectSubImage(r300ContextPtr rmesa,
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* Upload the texture image associated with texture \a t at the specified
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* level at the address relative to \a start.
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*/
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static void uploadSubImage( r300ContextPtr rmesa, r300TexObjPtr t,
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static void uploadSubImage( r300ContextPtr rmesa, r300TexObjPtr t,
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GLint hwlevel,
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GLint x, GLint y, GLint width, GLint height,
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GLuint face )
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{
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struct gl_texture_image *texImage = NULL;
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GLuint offset;
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GLint imageWidth, imageHeight;
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GLint ret;
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drm_radeon_texture_t tex;
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drm_radeon_tex_image_t tmp;
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const int level = hwlevel + t->base.firstLevel;
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struct gl_texture_image *texImage = NULL;
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GLuint offset;
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GLint imageWidth, imageHeight;
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GLint ret;
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drm_radeon_texture_t tex;
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drm_radeon_tex_image_t tmp;
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const int level = hwlevel + t->base.firstLevel;
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if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
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fprintf( stderr, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n",
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__FUNCTION__, (void *)t, (void *)t->base.tObj,
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level, width, height, face );
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}
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if ( RADEON_DEBUG & DEBUG_TEXTURE ) {
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fprintf( stderr, "%s( %p, %p ) level/width/height/face = %d/%d/%d/%u\n",
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__FUNCTION__, (void *)t, (void *)t->base.tObj,
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level, width, height, face );
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}
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ASSERT(face < 6);
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ASSERT(face < 6);
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/* Ensure we have a valid texture to upload */
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if ( ( hwlevel < 0 ) || ( hwlevel >= RADEON_MAX_TEXTURE_LEVELS ) ) {
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_mesa_problem(NULL, "bad texture level in %s", __FUNCTION__);
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return;
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}
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/* Ensure we have a valid texture to upload */
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if ( ( hwlevel < 0 ) || ( hwlevel >= RADEON_MAX_TEXTURE_LEVELS ) ) {
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_mesa_problem(NULL, "bad texture level in %s", __FUNCTION__);
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return;
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}
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texImage = t->base.tObj->Image[face][level];
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texImage = t->base.tObj->Image[face][level];
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if ( !texImage ) {
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: texImage %d is NULL!\n", __FUNCTION__, level );
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return;
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}
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if ( !texImage->Data ) {
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is NULL!\n", __FUNCTION__ );
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return;
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}
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if ( !texImage ) {
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: texImage %d is NULL!\n", __FUNCTION__, level );
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return;
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}
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if ( !texImage->Data ) {
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is NULL!\n", __FUNCTION__ );
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return;
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}
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if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
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assert(level == 0);
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assert(hwlevel == 0);
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is rectangular\n", __FUNCTION__);
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r300UploadRectSubImage( rmesa, t, texImage, x, y, width, height );
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return;
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}
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else if (texImage->IsClientData) {
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is in GART client storage\n",
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__FUNCTION__);
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r300UploadGARTClientSubImage( rmesa, t, texImage, hwlevel,
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x, y, width, height );
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return;
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}
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else if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is in normal memory\n",
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__FUNCTION__);
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if (t->base.tObj->Target == GL_TEXTURE_RECTANGLE_NV) {
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assert(level == 0);
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assert(hwlevel == 0);
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is rectangular\n", __FUNCTION__);
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r300UploadRectSubImage( rmesa, t, texImage, x, y, width, height );
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return;
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} else if (texImage->IsClientData) {
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if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is in GART client storage\n",
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__FUNCTION__);
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r300UploadGARTClientSubImage( rmesa, t, texImage, hwlevel,
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x, y, width, height );
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return;
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} else if ( RADEON_DEBUG & DEBUG_TEXTURE )
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fprintf( stderr, "%s: image data is in normal memory\n",
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__FUNCTION__);
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imageWidth = texImage->Width;
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imageHeight = texImage->Height;
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offset = t->bufAddr + t->base.totalSize / 6 * face;
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imageWidth = texImage->Width;
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imageHeight = texImage->Height;
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if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
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GLint imageX = 0;
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GLint imageY = 0;
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GLint blitX = t->image[face][hwlevel].x;
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GLint blitY = t->image[face][hwlevel].y;
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GLint blitWidth = t->image[face][hwlevel].width;
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GLint blitHeight = t->image[face][hwlevel].height;
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fprintf( stderr, " upload image: %d,%d at %d,%d\n",
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imageWidth, imageHeight, imageX, imageY );
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fprintf( stderr, " upload blit: %d,%d at %d,%d\n",
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blitWidth, blitHeight, blitX, blitY );
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fprintf( stderr, " blit ofs: 0x%07x level: %d/%d\n",
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(GLuint)offset, hwlevel, level );
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}
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offset = t->bufAddr + t->base.totalSize / 6 * face;
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t->image[face][hwlevel].data = texImage->Data;
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if ( RADEON_DEBUG & (DEBUG_TEXTURE|DEBUG_IOCTL) ) {
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GLint imageX = 0;
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GLint imageY = 0;
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GLint blitX = t->image[face][hwlevel].x;
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GLint blitY = t->image[face][hwlevel].y;
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GLint blitWidth = t->image[face][hwlevel].width;
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GLint blitHeight = t->image[face][hwlevel].height;
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fprintf( stderr, " upload image: %d,%d at %d,%d\n",
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imageWidth, imageHeight, imageX, imageY );
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fprintf( stderr, " upload blit: %d,%d at %d,%d\n",
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blitWidth, blitHeight, blitX, blitY );
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fprintf( stderr, " blit ofs: 0x%07x level: %d/%d\n",
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(GLuint)offset, hwlevel, level );
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}
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/* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
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* NOTE: we're always use a 1KB-wide blit and I8 texture format.
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* We used to use 1, 2 and 4-byte texels and used to use the texture
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* width to dictate the blit width - but that won't work for compressed
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* textures. (Brian)
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* NOTE: can't do that with texture tiling. (sroland)
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*/
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tex.offset = offset;
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tex.image = &tmp;
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/* copy (x,y,width,height,data) */
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memcpy( &tmp, &t->image[face][hwlevel], sizeof(tmp) );
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if (texImage->TexFormat->TexelBytes > 4) {
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const int log2TexelBytes = (3 + (texImage->TexFormat->TexelBytes >> 4));
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tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */
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tex.pitch = MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / 64, 1);
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tex.height = imageHeight;
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tex.width = imageWidth << log2TexelBytes;
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tex.offset += (tmp.x << log2TexelBytes) & ~1023;
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tmp.x = tmp.x % (1024 >> log2TexelBytes);
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tmp.width = tmp.width << log2TexelBytes;
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}
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else if (texImage->TexFormat->TexelBytes) {
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/* use multi-byte upload scheme */
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tex.height = imageHeight;
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tex.width = imageWidth;
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switch(texImage->TexFormat->TexelBytes) {
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case 1:
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tex.format = RADEON_TXFORMAT_I8;
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break;
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case 2:
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tex.format = RADEON_TXFORMAT_AI88;
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break;
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case 4:
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tex.format = RADEON_TXFORMAT_ARGB8888;
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break;
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}
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tex.pitch = MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / 64, 1);
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tex.offset += tmp.x & ~1023;
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tmp.x = tmp.x % 1024;
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t->image[face][hwlevel].data = texImage->Data;
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/* Init the DRM_RADEON_TEXTURE command / drm_radeon_texture_t struct.
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* NOTE: we're always use a 1KB-wide blit and I8 texture format.
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* We used to use 1, 2 and 4-byte texels and used to use the texture
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* width to dictate the blit width - but that won't work for compressed
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* textures. (Brian)
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* NOTE: can't do that with texture tiling. (sroland)
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*/
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tex.offset = offset;
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tex.image = &tmp;
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/* copy (x,y,width,height,data) */
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memcpy( &tmp, &t->image[face][hwlevel], sizeof(tmp) );
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if (texImage->TexFormat->TexelBytes > 4) {
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const int log2TexelBytes = (3 + (texImage->TexFormat->TexelBytes >> 4));
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tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */
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tex.pitch = MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / 64, 1);
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tex.height = imageHeight;
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tex.width = imageWidth << log2TexelBytes;
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tex.offset += (tmp.x << log2TexelBytes) & ~1023;
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tmp.x = tmp.x % (1024 >> log2TexelBytes);
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tmp.width = tmp.width << log2TexelBytes;
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} else if (texImage->TexFormat->TexelBytes) {
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/* use multi-byte upload scheme */
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tex.height = imageHeight;
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tex.width = imageWidth;
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switch(texImage->TexFormat->TexelBytes) {
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case 1:
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tex.format = RADEON_TXFORMAT_I8;
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break;
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case 2:
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tex.format = RADEON_TXFORMAT_AI88;
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break;
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case 4:
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tex.format = RADEON_TXFORMAT_ARGB8888;
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break;
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}
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tex.pitch = MAX2((texImage->Width * texImage->TexFormat->TexelBytes) / 64, 1);
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tex.offset += tmp.x & ~1023;
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tmp.x = tmp.x % 1024;
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if (t->tile_bits & R300_TXO_MICRO_TILE) {
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/* need something like "tiled coordinates" ? */
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tmp.y = tmp.x / (tex.pitch * 128) * 2;
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tmp.x = tmp.x % (tex.pitch * 128) / 2 / texImage->TexFormat->TexelBytes;
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tex.pitch |= RADEON_DST_TILE_MICRO >> 22;
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} else {
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tmp.x = tmp.x >> (texImage->TexFormat->TexelBytes >> 1);
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}
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#if 1
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if (t->tile_bits & R300_TXO_MICRO_TILE) {
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/* need something like "tiled coordinates" ? */
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tmp.y = tmp.x / (tex.pitch * 128) * 2;
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tmp.x = tmp.x % (tex.pitch * 128) / 2 / texImage->TexFormat->TexelBytes;
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tex.pitch |= RADEON_DST_TILE_MICRO >> 22;
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}
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else
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if ((t->tile_bits & R300_TXO_MACRO_TILE) &&
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(texImage->Width * texImage->TexFormat->TexelBytes >= 256) &&
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((!(t->tile_bits & R300_TXO_MICRO_TILE) && (texImage->Height >= 8)) ||
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(texImage->Height >= 16))) {
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/* weird: R200 disables macro tiling if mip width is smaller than 256 bytes,
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OR if height is smaller than 8 automatically, but if micro tiling is active
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the limit is height 16 instead ? */
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tex.pitch |= RADEON_DST_TILE_MACRO >> 22;
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}
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#endif
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{
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tmp.x = tmp.x >> (texImage->TexFormat->TexelBytes >> 1);
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}
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#if 1
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if ((t->tile_bits & R300_TXO_MACRO_TILE) &&
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(texImage->Width * texImage->TexFormat->TexelBytes >= 256) &&
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((!(t->tile_bits & R300_TXO_MICRO_TILE) && (texImage->Height >= 8)) ||
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(texImage->Height >= 16))) {
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/* weird: R200 disables macro tiling if mip width is smaller than 256 bytes,
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OR if height is smaller than 8 automatically, but if micro tiling is active
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the limit is height 16 instead ? */
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tex.pitch |= RADEON_DST_TILE_MACRO >> 22;
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}
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#endif
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}
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else {
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/* In case of for instance 8x8 texture (2x2 dxt blocks), padding after the first two blocks is
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needed (only with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */
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/* set tex.height to 1/4 since 1 "macropixel" (dxt-block) has 4 real pixels. Needed
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so the kernel module reads the right amount of data. */
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tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */
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tex.pitch = (R300_BLIT_WIDTH_BYTES / 64);
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tex.height = (imageHeight + 3) / 4;
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tex.width = (imageWidth + 3) / 4;
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if ((t->format & R300_TX_FORMAT_DXT1) == R300_TX_FORMAT_DXT1)
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{
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tex.width *= 8;
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} else {
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tex.width *= 16;
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}
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}
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} else {
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/* In case of for instance 8x8 texture (2x2 dxt blocks),
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padding after the first two blocks is needed (only
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with dxt1 since 2 dxt3/dxt5 blocks already use 32 Byte). */
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/* set tex.height to 1/4 since 1 "macropixel" (dxt-block)
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has 4 real pixels. Needed so the kernel module reads
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the right amount of data. */
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tex.format = RADEON_TXFORMAT_I8; /* any 1-byte texel format */
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tex.pitch = (R300_BLIT_WIDTH_BYTES / 64);
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tex.height = (imageHeight + 3) / 4;
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tex.width = (imageWidth + 3) / 4;
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if ((t->format & R300_TX_FORMAT_DXT1) == R300_TX_FORMAT_DXT1)
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{
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tex.width *= 8;
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} else {
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tex.width *= 16;
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}
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}
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LOCK_HARDWARE( &rmesa->radeon );
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do {
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ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE,
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&tex, sizeof(drm_radeon_texture_t) );
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if (ret) {
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if (RADEON_DEBUG & DEBUG_IOCTL)
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fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n");
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usleep(1);
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}
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} while ( ret == -EAGAIN );
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LOCK_HARDWARE( &rmesa->radeon );
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do {
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ret = drmCommandWriteRead( rmesa->radeon.dri.fd, DRM_RADEON_TEXTURE,
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&tex, sizeof(drm_radeon_texture_t) );
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if (ret) {
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if (RADEON_DEBUG & DEBUG_IOCTL)
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fprintf(stderr, "DRM_RADEON_TEXTURE: again!\n");
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usleep(1);
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}
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} while ( ret == -EAGAIN );
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UNLOCK_HARDWARE( &rmesa->radeon );
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UNLOCK_HARDWARE( &rmesa->radeon );
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if ( ret ) {
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fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret );
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fprintf( stderr, " offset=0x%08x\n",
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offset );
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fprintf( stderr, " image width=%d height=%d\n",
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imageWidth, imageHeight );
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fprintf( stderr, " blit width=%d height=%d data=%p\n",
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t->image[face][hwlevel].width, t->image[face][hwlevel].height,
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t->image[face][hwlevel].data );
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exit( 1 );
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}
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if ( ret ) {
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fprintf( stderr, "DRM_RADEON_TEXTURE: return = %d\n", ret );
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fprintf( stderr, " offset=0x%08x\n",
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offset );
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fprintf( stderr, " image width=%d height=%d\n",
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imageWidth, imageHeight );
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fprintf( stderr, " blit width=%d height=%d data=%p\n",
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t->image[face][hwlevel].width, t->image[face][hwlevel].height,
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t->image[face][hwlevel].data );
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exit( 1 );
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}
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}
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/**
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