Commit graph

201327 commits

Author SHA1 Message Date
Georg Lehmann
91f8e32a85 nir/opt_sink: do not sink inverse_ballot out of loops
Inverse_ballot result is undefined if the input is not dynamically uniform.
And sinking out of loops might make the input divergent.

Fixes: 18a0ff137f ("nir: sink/move inverse_ballot like moves")

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30906>
2024-09-12 21:49:34 +00:00
Georg Lehmann
1ec3cc2aed nir/opt_sink: do not sink load_ubo_vec4 out of loops
Same reason as for load_ubo.

Fixes: d199d65c3a ("nir/nir_opt_move,sink: Include load_ubo_vec4 as a load_ubo instr.")

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30906>
2024-09-12 21:49:34 +00:00
Kenneth Graunke
02482604e5 intel/brw: Delete old-style surface and A64 message opcodes
These have now been replaced by the MEMORY_*_LOGICAL opcodes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
7090578c35 intel/brw: Switch load_ubo_uniform_block_intel over to memory intrinsics
While there are many cases that turn into the *_PULL_CONSTANT_LOAD ops
or push constants, this one piece was emitting surface block loads.
Switch it over to use the new intrinsics to delete a bunch of code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
b55f77161d intel/brw: Switch to emitting MEMORY_*_LOGICAL opcodes
We introduce a new fs_nir_emit_memory_access() helper that can handle
image, bindless image, SSBO, shared, global, and scratch memory, and
handles loads, stores, atomics, and block loads.  It translates each
of these NIR intrinsics into the new MEMORY_*_LOGICAL intrinsics.

As a result, we delete a lot of similar surface access emitter code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
3ba97176d6 intel/brw: Switch load_num_workgroups to the new memory intrinsic
A simple case we handle directly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
dc4770b005 intel/brw: Lower MEMORY_OPCODE_*_LOGICAL to HDC messages
This is more complicated.  We map the MEMORY_*_LOGICAL opcodes to the
older HDC messages: typed and untyped surface read/write/atomic (whether
float or integer), DWord and Byte scattered messages, OWord block, and
both A64, BTI, and stateless messages.

- MEMORY_MODE_* is used to select stateless-scratch, typed, or untyped.
- MEMORY_FLAG_TRANSPOSE is used to select block access.
- MEMORY_BINDING_TYPE = FLAT and 64-bit address size selects A64.
- Alignment and data type size select between byte/dword scattered or
  surface messages.

While we may not be able to handle the full generality of message
possibilities, we can handle everything we generate currently.  The plan
here is to assert/validate that we don't generate MEMORY_*_LOGICAL ops
on HDC-based platforms which can't support those particular messages.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
3255c9cc49 intel/brw: Lower MEMORY_OPCODE_*_LOGICAL to LSC messages
This is pretty straightforward, as the new MEMORY_*_LOGICAL opcodes
are designed to match the new LSC's capabilities.  The main part is
constructing the message payload.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
a82e8b1c6b intel/brw: Pretty-print memory logical opcodes
The new MEMORY_*_LOGICAL intrinsics have a lot of control sources with
a bunch of LSC_* enums (opcode, memory type, address type, address and
data sizes), as well as flags, coordinate components vs. components...
they unfortunately are nigh-unreadable with the default printing since
there's just a string of unreadable UD immediates in some order.

To fix this, we add some basic pretty-printing.  If a control source is
simply an enum whose value communicates the entire purpose, we print it.
If it has a numeric value (i.e. alignment, or data), we add a label.

For example:

   memory_store(16) (null):UD store shared flat addr: %2:UD coord_comps:1u align:16u d32 comps:2u data0: %3:UD

   memory_store(16) (null):UD store typed bti:%2+0.0<0>:UD addr: %3+0.0:D coord_comps:2u align:0u d32 comps:4u data0: %4:UD

This make them much easier to read.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
2c67729386 intel/brw: Expose functions to convert LSC enums to strings
We had tables for these in the disassembler already, but I'd like to use
them in brw_print.cpp as well.  Just wrap the tables in convenience
functions we can use there.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
d5f38be713 intel/brw: Introduce new MEMORY_*_LOGICAL opcodes
This is a new unified set of opcodes for memory access loosely patterned
after the new LSC-style data port messages introduced on Alchemist GPUs.

Rather than creating an opcode for every type of memory access, it has
only three opcodes: load, store, and atomic.  It has various sources to
indicate the rest:

- Binding type (raw pointer, pointer to surface state, or BT index)
- Address size (A64, A32, A16)
- Data size (bit size, number of components)
- Opcode (atomic opcode, or LOAD/STORE vs. LOAD_CMASK/STORE_CMASK)
- Mode (typed vs. untyped vs. shared-local vs. scratch)
- Address (and its dimensionality)
- Data (0 for loads, 1 for stores, 2 for atomics)
- Whether we want block access

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
b8f264cfe4 intel/brw: Handle load/stores in lsc_op_for_nir_intrinsic()
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
8a6903e50d intel/brw: Rename lsc_aop_for_nir_intrinsic to "op" instead of "aop"
This is going to handle more than atomics shortly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
e8883bd40b intel/brw: Use size_written for NoMask instructions in is_partial_write
The intention of inst->is_partial_write() is that it should return true
when any REG_SIZE (32B) chunk of inst's destination is written but not
fully overwritten.  This can be used to tell whether inst combines new
data with existing data, or screens off any previous writes, so the old
values are no longer required.

The existing (exec_size * brw_type_size_bytes(this->dst.type) < 32)
check doesn't work in a number of cases.  For example, LSC block loads
have exec_size == 1 and force_writemask_all set, but may write multiple
full registers of data.  (Currently, we only see them with exec_size 1
after logical-send-lowering, so our SHADER_OPCODE_SEND special case
was covering those.)  We had also special cased UNDEF.

Instead, we can simply check:

   1. Predication
   2. !inst->dst.contiguous()
   3. inst->dst.offset % REG_SIZE != 0
   4. inst->size_written % REG_SIZE != 0

We had the first three already, but #4 is new.  If either #3 or #4
are true, then that implies there is a REG_SIZE chunk of the destination
which is written, but not entirely written, so it's a partial write.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Kenneth Graunke
ab0b9b6792 intel/brw: Use NUM_BRW_OPCODES in can_omit_write() check
The intention here is to detect ALU hardware instructions, but not
virtual instructions that haven't been explicitly whitelisted.

For some reason we had arbitrarily hardcoded 128 here, but our virtual
opcodes don't start at 128.  They start at NUM_BRW_OPCODES.  So, use
that instead.

This prevents regressions later when we delete some opcodes, shifting
some virtual opcodes into the 72-128 range.

Cc: mesa-stable
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30828>
2024-09-12 20:54:36 +00:00
Lars-Ivar Hesselberg Simonsen
0c18aa996b panfrost: Enable support for depth clamping
Depth clamping was not enabled in panfrost, leading to the fixed range
[0.0, 1.0] always being used.

This commit sets the bits to enable depth clamp to near/far plane
depending on the passed rasterizer state.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11506
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31041>
2024-09-12 20:04:58 +00:00
Lars-Ivar Hesselberg Simonsen
f5dab1b77e panfrost: Fix near/far depth clip
Near/far depth clip was implemented by setting the low/high_depth_clamp
to -/+INFINITY, which is invalid on Mali.

This commit removes the modification of the depth clamp values and
enables depth clipping by setting the depth_cull_enable state in the ZS
descriptor for v9+ (the equivalent pre-v9 RSD state is already set
correctly) and setting the primitive cull flags correctly for both.

Finally, it disables PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE for v9+, as
both plane clips are controlled by a single value.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11506
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31041>
2024-09-12 20:04:58 +00:00
Lars-Ivar Hesselberg Simonsen
5fd523fafb pan/genxml: Add pan_pack_nodefaults()
The new packing macro will not default initialize fields, which is
useful for structures used as override flags or in pan_merge().

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11506
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31041>
2024-09-12 20:04:58 +00:00
Lars-Ivar Hesselberg Simonsen
03c470d2ab panfrost: Move ForEachMacros into panfrost
This change moves panfrost specific ForEachMacros from the top level
.clang-format to the panfrost specific .clang-format.

This is done to avoid triggering CI for all drivers when making changes
to this list.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11506
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31041>
2024-09-12 20:04:58 +00:00
Boris Brezillon
387e6323f8 panvk/csf: Fix inverted address/destination register in CmdSetEvent2()
cs_load32_to() takes the destination register first, and the address
one next.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31147>
2024-09-12 19:29:08 +00:00
Boris Brezillon
a5c660d78a panvk/csf: Fix missing TSD pointer initialization on RUN_IDVS
The global thread storage descriptor can be allocated in the dispatch
path, which means the test on tsd != NULL might be true when the first
RUN_IDVS() happens, and we never set r24 to the TSD address.

Fix that by keeping a tsd field in panvk_cmd_graphics_state that's only
set in the draw path.

Reported-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Tested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Tested-by: Alexandre ARNOUD <aarnoud@me.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31147>
2024-09-12 19:29:08 +00:00
Daniel Stone
d8645aa03a ci/svga: Only run half the Piglit tests
The current runtime is quite a bit too long, so cut it in half.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31111>
2024-09-12 19:07:45 +00:00
Daniel Stone
8953c9b96f ci/svga: Add two Piglit flakes seen in the wild
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31111>
2024-09-12 19:07:45 +00:00
Daniel Stone
9c7cb49508 ci/windows: Increase dozen-deqp fraction
It takes far too long to run: bring it back down to something more
manageable.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31111>
2024-09-12 19:07:45 +00:00
Daniel Stone
0f6be273f1 doc/vc4: Remove reference to old shader-db
Piglit has the traces now.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31111>
2024-09-12 19:07:45 +00:00
Daniel Stone
d8839b2548 doc/linkcheck: Exclude cgit.fd.o
It's no more.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31111>
2024-09-12 19:07:44 +00:00
Daniel Stone
ebd45f0e64 docs/gallium: Fix broken GL extension link
The :ext: macro doesn't know that astc_ldr is actually defined in the
astc_hdr spec doc.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31111>
2024-09-12 19:07:44 +00:00
Daniel Stone
3b2d85d213 doc/llvmpipe: Fix broken link syntax
Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: 13a2805325 ("llvmpipe: FlameGraph profiling support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31111>
2024-09-12 19:07:44 +00:00
Daniel Stone
dd5d737e6c ci/lava: Use new pyutils container
Instead of unpacking the x86_64_build container and its billion build
dependencies every time, switch to using only what's in the minimal
pyutils container, and the Python scripts we get as an artifact from the
python-test job. Pulling the artifacts from S3 rather than using GitLab
is also much more efficient.

This should substantially reduce the runtime required to get to testing.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31151>
2024-09-12 18:17:52 +00:00
Daniel Stone
4ee55568b7 ci/python: Allow empty PYTHONPATH
$PYTHONPATH doesn't have to be set, so let it expand to nothing if
there's nothing there.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31151>
2024-09-12 18:17:52 +00:00
Daniel Stone
51c2707b8e ci: Add pyutils container
Currently, our jobs which only want to run a little bit of python -
python-test and the LAVA jobs - pull the entire x86_64-build image,
which is both massive, and massively unnecessary.

Create a separate image which only carries what we need to run our
Python tests and utilities, and switch python-test to using that.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31151>
2024-09-12 18:17:52 +00:00
Daniel Stone
4ad94366c3 ci: Add Python requirements include
Make it so we can install everything we need with just
pip3 -r bin/ci/test/requirements.txt.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31151>
2024-09-12 18:17:52 +00:00
Daniel Stone
3a59398fad ci/lima: Temporarily disable
The caching proxy is returning 404 for the job overlay.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31154>
2024-09-12 18:14:00 +00:00
David Heidelberg
e4b247ec9b ci/intel: Officially switch intel-adl-cl to pre-merge
It has proven to be useful.

Due to the .rusticl-rules reference, job was already running in pre-merge,
so let's make it official.

Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31144>
2024-09-12 15:40:03 +00:00
Sil Vilerino
0c8fa50dfa d3d12: Support create_dpb_buffer for non-opaque allocations when decoder/encoder supports it
Note that D3D12_VIDEO_ENCODER_SUPPORT_FLAG_READABLE_RECONSTRUCTED_PICTURE_LAYOUT_AVAILABLE
was added in DirectX-Headers v1.614.1

Reviewed-By: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31092>
2024-09-12 15:01:18 +00:00
Sil Vilerino
702bd657cc ci: Bump DirectX-Headers and Agility SDK dependencies to 1.614.1
Reviewed-By: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31092>
2024-09-12 15:01:18 +00:00
Juan A. Suarez Romero
8338e2082e v3d: do not rebind a sampler view already rebound
As sampler view can be used multiple times, do not attempt to rebind if
it was already bound.

This fixes a crash when replaying half-life-2-v2.trace.

Backport-to: 24.2
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31049>
2024-09-12 14:36:56 +00:00
Juan A. Suarez Romero
c84be162a1 Revert "v3d: never replace a mapped bo"
This reverts commit 0b85476d86.

When mapping a BO in v3d, the map keeps forever until freeing the BO. If
later the map is required again, we reuse the map instead of doing the
map from scratch.

This saves calling map/unmap continuously, as well as a mechanism to
keep control of the map usage, like a reference count.

Thus, when reallocating a BO, if it is mapped it just means the map was
used in the past, but not necessarily it is in use right now.

The reverted commit was causing performance regressions in multiple
applications, reducing from 60fps to 5fps.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11783
Backport-to: 24.2
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31049>
2024-09-12 14:36:56 +00:00
Juan A. Suarez Romero
fed73edf16 v3d/ci: add new flake for rpi5
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31146>
2024-09-12 13:03:06 +02:00
Samuel Pitoiset
e1df6cf499 radv: use radv_get_user_sgpr_loc() more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31115>
2024-09-12 07:01:36 +00:00
Samuel Pitoiset
190d46b65d radv: precompute more PGM registers for all stages
Less error prone and easier to update for new hardware.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31115>
2024-09-12 07:01:36 +00:00
Samuel Pitoiset
c7a509f55c radv: update PGM register for TES+GS compiled separately with ESO
Not sure why 0xB210 works on GFX10+ because it's supposed to be
0xB320 with/without NGG...

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31115>
2024-09-12 07:01:36 +00:00
Martin Roukala (né Peres)
97624f99a1 radv/ci: run vkcts-navi31-valve pre-merge
We currently have 3 runners with 7950X3D CPUs and 7900XT GPUs which
can rip through VKCTS in ~16 minutes.

Since this is over the 15 minutes threshold, we parallelize the job to
get under 15 minutes, which nets up ~10 minutes total runtime.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31085>
2024-09-12 03:37:18 +00:00
Martin Roukala (né Peres)
09892aec09 zink/ci: document more flakes
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31085>
2024-09-12 03:37:18 +00:00
Martin Roukala (né Peres)
7bb80e184c radv/ci: document more vkcts flakes
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31085>
2024-09-12 03:37:18 +00:00
Dave Airlie
7c6e3c70b6 radv/video/enc: report pps overrides in feedback for h265
radv does change h265 usually so report in feedback info.

Fixes: 967e4e09de ("radv/video: add h265 encode support")
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31135>
2024-09-12 10:58:02 +10:00
Dave Airlie
8d08e92199 radv/video: fix encode reference slot counting
This needs the max of slot indices.

Fixes: 54d499818c ("radv/video: add initial support for encoding with h264.")
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31135>
2024-09-12 10:57:58 +10:00
Dave Airlie
e89f4a48fd radv: Fix radeon_enc_code_ue with values over 2^16
This ports this fixes from radeonsi:

138ba42a87 ("radeonsi/vcn: Fix radeon_enc_code_ue with values over 2^16")

Cc: mesa-stable
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31135>
2024-09-12 10:57:18 +10:00
Nanley Chery
e0157abec6 anv,iris: Pack depth pixels into initialized arrays
Coverity alerts that the uint32_t pointer I was passing into
isl_color_value_pack() could possibly be used as an array. The value is
being used as such, but only the first element of that array should be
accessed. That's because the depth buffer formats I'm also passing into
the function only have a single channel, R. Nonetheless, let's update
the code to avoid the warning.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31123>
2024-09-11 22:04:30 +00:00
Mike Blumenkrantz
bb16203a8d zink: fix sparse bo deallocation
this loop was not correctly iterating the dynarray

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31124>
2024-09-11 21:07:45 +00:00