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Author SHA1 Message Date
Caio Oliveira
2251748aad intel/brw: Add dst/srcs register numbers to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
808b8b65b6 intel/brw: Add abs/negate to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
f6dbb72219 intel/brw: Add dst/src0 address_mode to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
e4440df2d8 intel/brw: Add pred/cmod/sat to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
be70d1f9b1 intel/brw: Add dst/srcs type to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
e0ba4ca166 intel/brw: Add dst/srcs reg file to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
3db1c3fc0e intel/brw: Add access_mode to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
3dc1f64e51 intel/brw: Add exec_size to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
853fe03470 intel/brw: Add has_dst to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
c394eb3111 intel/brw: Add num_sources to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
9cdb90e787 intel/brw: Add opcode to brw_hw_decoded_inst 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
76e177d87d intel/brw: Create a struct to hold a decoded brw_inst in eu_validation 
For now it contains only the "raw" brw_inst.  Later patches will add
useful fields to it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Caio Oliveira
382bd4ce36 intel/brw: Add ERROR helper variant that returns to EU validation 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
 2024-10-11 04:13:48 +00:00
Faith Ekstrand
2fb4aed9d8 nvk: Advertise VK_KHR_fragment_shading_rate 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
e45effe555 nvk: Set VARIABLE_PIXEL_RATE_SHADING_TABLE_SELECT 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
99107ef8d4 nak: Add support for gl_PrimitiveShadingRateEXT 
This aliases gl_ViewportIndex in the NVIDIA attribute space.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
ab8e6bf4c3 nak: Pass a nak_compiler into sysval and attrib helpers 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
58252622f1 nak: Add support for gl_ShadingRateEXT 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
957a1add26 nak: Rename SV_VERTEX_COUNT to PRIM_TYPE 
This is what nvdisasm calls it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
1e7c3ddc33 nak: Get rid of some dead code warnings 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
75bcb656d9 nvk: Add support for binding fragment shading rate images 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
16bd3f0f50 nvk: Emit FSR state 
This is mostly a matter of filling out the
VARIABLE_PIXEL_SHADING_INDEX_TO_RATE tables.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
55854de584 nvk: Rework setting of min_sample_shading 
Instead of just storing a pre-computed min_sample_shading, store both
sample_shading_enable and min_sample_shading and then compute the final
min_sample_shading value when we emit state.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
746ea7b0cd vulkan: Add a vk_fragment_shading_rate_is_disabled() helper 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
29dd0236b5 nvk: Initialize VARIABLE_PIXEL_RATE_SAMPLE_ORDER 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
840ec73f51 nvk: Implement GetPhysicalDeviceFragmentShadingRatesKHR() 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
8f1697b12d nil: Use D3D sample modes by default 
Only the D3D modes work with RASTER_SAMPLES_MODE or with variable
shading rates.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
e14b4bcb88 nvk: Support D3D sample modes 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
097f8b2c7d nil: Add D3D sample layouts 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
279cebf726 nouveau/class_parser: Add more method arrays 
A bunch of FSR stuff is arrays.  While we're at it, add a handful of
other things I've seen in blob traces.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
48898c47bf nvk: Rework setup of sample masks 
Annoyingly, 2x2 with 2 passes uses the masks 0xa and 0x5, not 0x3 and
0xc as the current code assumes.  When we enable 4x2_D3D, that one gets
even more wonky.  This reworks things so that we have two copies of root
descriptor sample_masks array in scratch states, one for 2pass and one
for 4pass, that get copied into the push constants as needed.  This
should handle the needs of both 2x2 and 4x2_D3D as well as 4x4 when the
time comes.

Fixes: 6a84d5439d ("nvk: Move the ANTI_ALIAS_CONTROL logic to the MME")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
f009721d11 nvk: Add an nvk_cmd_emit_sample_layout() helper 
This also pulls SET_ANTI_ALIAS and MME_SET_ANTI_ALIAS together.

Fixes: 6a84d5439d ("nvk: Move the ANTI_ALIAS_CONTROL logic to the MME")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
f8c0377421 nil: Add a helper to get samples from a SampleLayout 
Fixes: 6a84d5439d ("nvk: Move the ANTI_ALIAS_CONTROL logic to the MME")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
cf31388a9a nouveau/mme: Turing can't have emit and state in the same op 
Fixes: 6a84d5439d ("nvk: Move the ANTI_ALIAS_CONTROL logic to the MME")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:57 +00:00
Faith Ekstrand
095db78474 nouveau/mme: Evaluate methods immediately in the Turing sim 
Fixes: 6a84d5439d ("nvk: Move the ANTI_ALIAS_CONTROL logic to the MME")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:56 +00:00
Faith Ekstrand
f380136c1d nouveau/mme: Test ifs with immediate parameters 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31585>
 2024-10-10 23:16:56 +00:00
Daniel Stone
3dcb6a0f23 egl/x11: Downgrade warning to info 
This warning is emitted 10,074 times during a virpipe-on-gl job. Let's
emit it zero times.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31591>
 2024-10-10 20:52:02 +00:00
David Heidelberg
ace38d8432 ci: restrict number of maximum threads 
This makes LTO non-abusive to the servers.

Suggested-by: psykose <alice@ayaya.dev>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28684>
 2024-10-10 19:19:54 +00:00
David Heidelberg
afab416be4 ci: enable IPO/LTO only for nightly builds 
1. nightly takes a long, the extra few minutes for linking don't matter
2. nightly will run faster, since where it's CPU dependent it's at least +5% perf
3. it may reveal some painful areas of common code or driver.
4. for some jobs (not enabled yet, it generates ugly errors, disable
   there

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28684>
 2024-10-10 19:19:54 +00:00
David Heidelberg
2630e3e47a ci/fedora: when doing non-LTO build, we need C_ARGS too 
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28684>
 2024-10-10 19:19:54 +00:00
Karol Herbst
9cdf897c5e rusticl: allow asahi to be enabled by default 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31589>
 2024-10-10 18:24:31 +00:00
Karol Herbst
767695b2c4 asahi: implement get_cl_cts_version 
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31589>
 2024-10-10 18:24:31 +00:00
Jose Maria Casanova Crespo
687ed3fcaa v3d: initialize job local key with the 8 color buffer available in v7.1+ 
Fixes: 9e90d95508 ("v3d,v3dv: support up to 8 render targets in v7.1+")

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31582>
 2024-10-10 16:44:58 +00:00
Samuel Pitoiset
583b93f7a2 radv: rename 'gfx' to 'main' in the DGC path 
It can be confusing because the main DGC IB can be executed either on
GFX or ACE compute queues.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31583>
 2024-10-10 15:52:51 +00:00
Rhys Perry
33eb2d7fe4 aco: skip uniformization of certain merge phis 
If a source is a VGPR, then skip if it's safe. This fixes the regressions
from the previous commit.

fossil-db (navi31):
Totals from 5118 (6.45% of 79395) affected shaders:
MaxWaves: 159560 -> 159520 (-0.03%); split: +0.01%, -0.03%
Instrs: 2165351 -> 2138456 (-1.24%); split: -1.26%, +0.02%
CodeSize: 11260340 -> 11152460 (-0.96%); split: -0.98%, +0.02%
VGPRs: 218124 -> 225144 (+3.22%); split: -0.13%, +3.35%
Latency: 11059208 -> 11116102 (+0.51%); split: -0.18%, +0.69%
InvThroughput: 1252148 -> 1230193 (-1.75%); split: -1.77%, +0.01%
VClause: 39513 -> 39518 (+0.01%); split: -0.48%, +0.49%
SClause: 59434 -> 59378 (-0.09%); split: -0.11%, +0.02%
Copies: 165997 -> 156172 (-5.92%); split: -6.68%, +0.76%
PreSGPRs: 181203 -> 181094 (-0.06%)
PreVGPRs: 139393 -> 139731 (+0.24%)
VALU: 1244301 -> 1220769 (-1.89%); split: -1.91%, +0.02%
SALU: 200240 -> 199567 (-0.34%); split: -0.34%, +0.00%

fossil-db (navi21):
Totals from 35520 (44.74% of 79395) affected shaders:
MaxWaves: 951870 -> 951830 (-0.00%)
Instrs: 20229388 -> 20227776 (-0.01%); split: -0.01%, +0.00%
CodeSize: 105379916 -> 105513740 (+0.13%); split: -0.01%, +0.13%
VGPRs: 1375232 -> 1375400 (+0.01%)
Latency: 81046435 -> 81013986 (-0.04%); split: -0.04%, +0.00%
InvThroughput: 15269166 -> 15273295 (+0.03%); split: -0.01%, +0.04%
VClause: 354314 -> 354310 (-0.00%); split: -0.00%, +0.00%
SClause: 417049 -> 417047 (-0.00%); split: -0.00%, +0.00%
Copies: 1699445 -> 1699488 (+0.00%); split: -0.01%, +0.01%
Branches: 591274 -> 591269 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 1371062 -> 1370567 (-0.04%)
PreVGPRs: 1100716 -> 1100953 (+0.02%)
VALU: 11076189 -> 11075167 (-0.01%); split: -0.01%, +0.00%
SALU: 3648002 -> 3647378 (-0.02%); split: -0.02%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30211>
 2024-10-10 14:59:27 +00:00
Rhys Perry
ce33ffd03a aco: ensure phis uniformized by divergence analysis are SGPR 
Otherwise, they might not actually be uniform when divergence analysis
claimed they are.

fossil-db (navi31):
Totals from 5118 (6.45% of 79395) affected shaders:
MaxWaves: 159520 -> 159560 (+0.03%); split: +0.03%, -0.01%
Instrs: 2138456 -> 2165351 (+1.26%); split: -0.02%, +1.28%
CodeSize: 11152460 -> 11260340 (+0.97%); split: -0.02%, +0.98%
VGPRs: 225144 -> 218124 (-3.12%); split: -3.25%, +0.13%
Latency: 11116102 -> 11059208 (-0.51%); split: -0.69%, +0.18%
InvThroughput: 1230193 -> 1252148 (+1.78%); split: -0.01%, +1.80%
VClause: 39518 -> 39513 (-0.01%); split: -0.49%, +0.48%
SClause: 59378 -> 59434 (+0.09%); split: -0.02%, +0.11%
Copies: 156172 -> 165997 (+6.29%); split: -0.81%, +7.10%
PreSGPRs: 181094 -> 181203 (+0.06%)
PreVGPRs: 139731 -> 139393 (-0.24%)
VALU: 1220769 -> 1244301 (+1.93%); split: -0.02%, +1.95%
SALU: 199567 -> 200240 (+0.34%); split: -0.00%, +0.34%

fossil-db (navi21):
Totals from 35520 (44.74% of 79395) affected shaders:
MaxWaves: 951830 -> 951870 (+0.00%)
Instrs: 20227773 -> 20229388 (+0.01%); split: -0.00%, +0.01%
CodeSize: 105513724 -> 105379916 (-0.13%); split: -0.13%, +0.01%
VGPRs: 1375400 -> 1375232 (-0.01%)
Latency: 81013985 -> 81046435 (+0.04%); split: -0.00%, +0.04%
InvThroughput: 15273291 -> 15269166 (-0.03%); split: -0.04%, +0.01%
VClause: 354310 -> 354314 (+0.00%); split: -0.00%, +0.00%
SClause: 417047 -> 417049 (+0.00%); split: -0.00%, +0.00%
Copies: 1699486 -> 1699445 (-0.00%); split: -0.01%, +0.01%
Branches: 591269 -> 591274 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1370567 -> 1371062 (+0.04%)
PreVGPRs: 1100953 -> 1100716 (-0.02%)
VALU: 11075164 -> 11076189 (+0.01%); split: -0.00%, +0.01%
SALU: 3647378 -> 3648002 (+0.02%); split: -0.00%, +0.02%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30211>
 2024-10-10 14:59:26 +00:00
Rhys Perry
67ad7359ff nir/divergence_analysis: disable phi undef optimization by default 
If the backend does not implement this too, or some other future transform
modifiess the phi so that this isn't the case (replace the phi with a
bcsel or replace undef with zero), then it will not actually be uniform.

This keeps it enabled to some degree for RADV/ACO.

fossil-db (navi31):
Totals from 76 (0.10% of 79395) affected shaders:
Instrs: 195008 -> 195282 (+0.14%)
CodeSize: 1012592 -> 1015884 (+0.33%)
Latency: 3892826 -> 3898843 (+0.15%); split: -0.00%, +0.15%
InvThroughput: 460681 -> 460964 (+0.06%)
Copies: 13508 -> 13516 (+0.06%)
Branches: 5244 -> 5412 (+3.20%)
PreVGPRs: 5092 -> 5096 (+0.08%)
VALU: 116177 -> 116197 (+0.02%)
SALU: 23449 -> 23785 (+1.43%)

fossil-db (navi21):
Totals from 76 (0.10% of 79395) affected shaders:
Instrs: 164471 -> 164981 (+0.31%)
CodeSize: 883988 -> 888420 (+0.50%)
Latency: 4074287 -> 4082043 (+0.19%)
InvThroughput: 783783 -> 784276 (+0.06%); split: -0.00%, +0.06%
Branches: 5262 -> 5430 (+3.19%)
PreVGPRs: 5100 -> 5104 (+0.08%)
VALU: 116375 -> 116381 (+0.01%)
SALU: 23589 -> 23925 (+1.42%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30211>
 2024-10-10 14:59:26 +00:00
Samuel Pitoiset
2643c48700 radv/amdgpu: remove unused code about external IBs in the submit path 
Now that everything is chained, the driver no longer uses external IBs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
 2024-10-10 14:08:39 +00:00
Samuel Pitoiset
d686ba36a9 radv/amdgpu: simplify cs_execute_ib() 
It's only used for executing IB2 on GFX.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
 2024-10-10 14:08:39 +00:00
Samuel Pitoiset
c1b2cb6ef7 radv: implement IB chaining for DGC when it's executed on compute 
The IB2 packet is only supported on the graphics queue. To execute DGC
IB on compute, the previous solution was to submit it separately
without any chaining. Though this solution was incomplete because it's
easy to reach the maximum number of IBs per submit when there is a lot
of ExecuteIndirect() calls.

To fix that, the proposed solution is to implement DGC IB chaining when
it's executed on the compute only. The idea is to add a trailer that is
added at the beginning of the DGC IB (to know the offset). This trailer
is used to chain back back the DGC IB to a normal CS, it's patched at
execution time. Patching is fine because it's not allowed to execute
the same DGC IB concurrently and the entire solution relies on that.

When the DGC IB is executed on graphics, the trailer isn't patched and
it only contains NOPs padding. Performance should be mostly similar.

This fixes
dEQP-VK.dgc.nv.compute.misc.execute_many_*_primary_cmd_compute_queue.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
 2024-10-10 14:08:39 +00:00